Omar James Bchir

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

An innovative packaging solution — ‘Cu-column on BOL’ (CuBOL) is developed that dramatically reduces flip chip package cost and offers superior product reliability, thus posing an important flip chip package solution in mobile product applications. The CuBOL technology, utilizing the fcCuBE™ offering by STATS ChipPAC, entails proprietary changes in the bump interconnect structure using Cu-column bump attached to a narrow trace or bond-on-lead (BOL) on substrate without any solder resist confinement (open SR) in the peripheral I/O region of the die. This enables improved routing efficiency on the substrate top layer thus allowing conversion of a flip chip substrate from original 4L to 2L without compromising functionality. The cost of the flip chip package is lowered by means of reduced substrate layer count, removal of solder on pad (SOP) and solder mask and relaxed design rules. When combined with high density substrate strip design and molded underfill (MUF), this process further lowers the manufacturing cost. Use of Cu-column bump with Pb-free solder cap used in CuBOL technology helps achieve a ‘Green’ package solution, which is complimented by improved package reliability benefits achieved by a remarkable reduction of package stress due to the resulting interconnect structure. The CuBOL technology has also been proven to protect the extreme or ultra low K (ELK/ULK) die-electric against cracking or delamination as confirmed with empirical data generated using advanced silicon node test vehicles and further substantiated by thermo-mechanical simulation results. This paper summarizes the multidisciplinary effort undertaken to develop and qualify CuBOL technology using a 7×7 mm fcTFBGA package as test vehicle (TV). Existing substrate design in a 1–2–1 laminate build-up substrate was comfortably routed into 2 layer substrate design, yet maintaining the I/O count, original bump lay-out & ball map and the original bump-to-ball netlist by applying more efficient routing scheme offered by CuBOL technology. TV wafers were bumped using the composite structure of Cu-column with a Pb-free solder cap. Different aspect ratio of Cu-column height to solder cap height were evaluated to find the optimal one to ensure robust joint formation. Flip chip attach process using composite Cu-column bump with narrow BOL pad was studied in detail in terms of impact of design, and process factors on non-wet, solder short and warpage performance. Side by side comparison of original 4L design and CuBOL 2L was conducted in terms of strip and unit warpage finding significant benefits with the latter. Ultimately, extensive reliability testing was conducted on the packaged units assembled using CuBOL technology by subjecting through a battery of JEDEC standard stress tests for example — preconditioning, temperature cycling (TC), high temperature storage(HTS) and un-biased HAST and excellent reliability results with adequate margins were obtained. Subsequent interception of CuBOL technology into advanced silicon node TVs showed improved package reliability with ELK stress reduction. This finding was further substantiated using thermo-mechanical simulation studies comparing CuBOL interconnect structure with control leg, thus proving CuBOL to be a superior interconnect structure for ELK protection. Finally, electrical performance assessment studies done to ensure product functionality parity between CuBOL design with reduced layer count with the original product design is also presented in this paper.

Improvement of substrate and package warpage by copper plating process optimization

High substrate warpage can lead to unacceptable yield loss during chip attach in assembly, and cause high yield fallout during package mount on the circuit board. For the first time, through this work, the electrolytic copper (Cu) plating process in substrate manufacturing was shown to contribute significantly to package warpage. For a 14×14mm package, reducing the Cu plating rate (within the manufacturing operating window) resulted in 21% package warpage reduction, while a change in Cu plating solution provided an additional 6% reduction (total 27% reduction). Hence the Cu plating process and solution must be carefully scrutinized to minimize package warpage, specifically for thin packages (<;1mm) where Cu stresses become a large contributing factor.

The electromigration behavior of copper pillars for different current directions and pillar shapes

A significant asymmetry in electromigration behavior was observed for copper pillars depending on the electron current direction; the electromigration performance is very robust for an electron source at the die-side, but vulnerable to the opposite electron flow direction. Through extensive failure analysis, it was observed that die-side electron source leads to a stable layering of intermetallic compounds and no electromigration-induced voiding, while the substrate-side electron source leads to more extensive transformation into intermetallic compounds at the expense of the copper trace as well as electromigration-induced voiding. These phenomena were exacerbated by narrower trace widths but improved by an oblong pillar shape. Further, the presence of a nickel cap between the solder and pillar did not significantly impact electromigration lifetime.