Osama Khouri

High-voltage management in single-supply CHE NOR-type flash memories

In a flash memory, a number of voltage levels different from V/sub DD/ are needed to perform the required operations (read, program, and erase) on the array cells. In the case of single-supply memory devices, voltages higher than V/sub DD/ as well as negative voltages, which are referred to as high voltages (HVs), must be produced on-chip. This paper aims at giving the reader an overview of how HVs are generated and managed in single-supply NOR-type flash memories programmed by channel hot-electron injection. Both schemes used for conventional (i.e., bilevel) memory devices and schemes designed to meet multilevel memory requirements are addressed.

Improved charge pump for flash memory applications in triple well CMOS technology

Flash memories, which are key components for non-volatile storage in many portable applications, require high voltages for correct operation. These voltage have to be generated by using on-chip voltage elevators. This article presents an improved scheme for charge-pump voltage elevators suitable for use in triple-well CMOS fabrication technology. A direct drain-bulk connection is realized for the pass transistor which implements the charge transfer device in each pump stage. This results in placing a P-N diode in parallel with the pass transistor, thereby improving the charge transfer process between adjacent stages. The proposed charge pump provides smaller output resistance (and, hence, larger current drive capability and shorter recovery time) and higher power efficiency as compared to conventional solutions. An experimental comparison between two charge pump modules (based on the traditional and on the presented scheme, respectively) integrated in 0.13-μm CMOS Flash technology, demonstrated the effectiveness of the proposed approach.

Program and Verify Word-Line Voltage Regulator for Multilevel Flash Memories

This paper presents a word-line voltage generator for multilevel (ML) Flash memory programming. The required voltages are provided by a regulator supplied by an on-chip charge-pump voltage multiplier. A feedback loop including a digitally programmable resistive divider generates the staircase-shaped waveform needed for adequate ML programming accuracy as well as the read/verify voltage required for read and verify operations. A high-swing controlled-discharge circuit minimizes the settling time when switching from program to verify phases and vice versa. The same generator is used to provide the voltage required in read and in program mode, thus saving silicon area and minimizing current consumption. Experimental results of the proposed circuit integrated in a 4-level-cell 64-Mb NOR-type Flash memory are presented.