Stefano Gregori

On-chip error correcting techniques for new-generation flash memories

In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.

Protection Circuit against Differential Power Analysis Attacks for Smart Cards

In this paper, we present a circuit that protects smart cards against differential power analysis attacks. The circuit is based on a current flattening technique, is designed using a standard 0.18-mum CMOS technology, and can be integrated on the same die or in the same package with the smart card microcontroller. We evaluate the current flattening performance and the effectiveness of the protection against differential power analysis attacks. Our analysis is based on transistor-level simulations in Cadence environment using experimental current traces collected from an 8-bit microcontroller for smart cards executing DES encryptions. The proposed circuit effectively protects against differential power analysis attacks with small chip area overhead and limited increased power consumption during the encryption cycles.

An adaptive QoS and energy-aware routing algorithm for wireless sensor networks

As wireless sensor networks (WSNs) increasingly attract more attention, new ideas for specific applications are continually being developed, many of which involve the energy consumption of nodes. However, not much has been done to optimize the quality of services (QoS) of WSNs. Many applications like target tracking require some QoS guarantees. Besides, certain factors limit the ability of multi-hop sensor networks to achieve desired goals such as the delay caused by network congestion, limited energy and computation of sensor nodes, packet loss due to interferences and mobility. In this paper, an adaptive QoS and energy-aware routing approach is proposed using an improved ant colony algorithm for WSNs to not only meet QoS requirements in an energy-aware fashion, but also balance the node energy utilization to maximize the network lifetime. Extensive simulation results under various experimental settings demonstrated the effectiveness of the proposed algorithm in terms of packet delivery rate, load balance, and the delay in comparison to the existing state-of-the-art directed diffusion routing algorithm.

A performance comparison of dickson and fibonacci charge pumps

This paper presents an analysis of two types of integrated charge pumps, Dickson and Fibonacci. The two circuits are compared in slow-switching conditions and at equal area occupation. A formula is developed for optimizing the capacitor sizes and improving the performance of the Fibonacci charge pump. The performance is evaluated with focus on voltage gain and output resistance and including the effects of parasitic capacitances.

Improved charge pump for flash memory applications in triple well CMOS technology

Flash memories, which are key components for non-volatile storage in many portable applications, require high voltages for correct operation. These voltage have to be generated by using on-chip voltage elevators. This article presents an improved scheme for charge-pump voltage elevators suitable for use in triple-well CMOS fabrication technology. A direct drain-bulk connection is realized for the pass transistor which implements the charge transfer device in each pump stage. This results in placing a P-N diode in parallel with the pass transistor, thereby improving the charge transfer process between adjacent stages. The proposed charge pump provides smaller output resistance (and, hence, larger current drive capability and shorter recovery time) and higher power efficiency as compared to conventional solutions. An experimental comparison between two charge pump modules (based on the traditional and on the presented scheme, respectively) integrated in 0.13-μm CMOS Flash technology, demonstrated the effectiveness of the proposed approach.

Monolithic DC-DC boost converter with current-mode hysteretic control

A monolithic DC-DC boost converter with current-mode hysteretic control is designed and simulated in 0.18-μm CMOS technology. The system is simple, robust, and has a fast response to external changes. It does not require an external clock, and the output is regulated by voltage feedback in addition to limiting the inductor current by sensing it. A non-overlapping clock is internally generated to drive the power switches using buffers designed to minimize power dissipation. For conversion specifications of 1.8 V to 3.3 V at 150 mA, overall efficiency of 94.5% is achieved. Line regulation is 17.5 mV/V, load regulation is 0.33% for a 100 mA current step, while the output voltage ripple is below 30 mV for nominal conditions.

Real-time Monitoring System for Odours around Livestock Farms

A sensor network-based livestock farm odour monitoring system is proposed for monitoring and analyzing livestock farm odour remotely. The system utilizes a wireless sensor network built from electronic nose nodes which can detect odour compounds and environment factors such as temperature and humidity. The architecture of the system and the functionality of each component is introduced. The proposed odour monitoring system can provide farmers and researchers with more precise odour management capabilities for more efficient operation of odour reduction systems such as ventilation fans. It can aid the development of an optimal overall odour management strategy by providing real-time, detailed data about the livestock farm environment and odour dispersion.

On-chip current flattening circuit with dynamic voltage scaling

This paper presents the circuit-level implementation for a current flattening system designed to control the power-supply current and to protect cryptosystems from power analysis attacks. When required, the proposed circuit dynamically controls the power consumption by injecting an extra current and by scaling the power-supply voltage. The circuit can be integrated on the same chip with a cryptographic processor. In this way the power-supply current has little meaningful information for a side-channel attack. The proposed circuit has been designed in a 0.18 mum CMOS technology and operates with a nominal 1.8-V power supply

An integrated current flattening module for embedded cryptosystems

In embedded cryptosystems, the variation of current or power consumption might be the point of attack on confidentiality because of the dependency of power consumption on the data and algorithms. This paper presents a real-time current flattening module that controls dynamically the power consumption of a cryptosystem. The module together with specialized cryptographic hardware can be integrated on the same chip. In this way, the output current of the cryptographic system has little discernable information for a side-channel attack. The real-time current flattening module is designed in this paper using 0.18 /spl mu/m CMOS technology and operates at 1.8 V power supply.

Charge reusing in switched-capacitor voltage multipliers with reduced dynamic losses

In this work we study the application of charge reusing to switched-capacitor voltage multipliers. Considering three popular circuits (i.e. the Dickson, the heap, and the Fibonacci charge pumps), we analyze the dynamic power losses due to parasitic capacitances. We show how a charge reuse technique effectively decreases the dynamic power losses. The validity of our analysis is verified through simulations of design examples, which also illustrate the impact of charge reusing on voltage gain, output resistance, and conversion efficiency.