Osamu Kudoh

A 15 ns 4 Mb CMOS SRAM

A 4-Mb SRAM with 15-ns access time and selectable (*4/*1) bit organization based on a 0.55- mu m triple-polysilicon double-metal CMOS technology is discussed. To achieve 15-ns access time, a sense amplifier with input-controlled PMOS loads (ICPLs), Y-controlled bit line loads, and transfer word driver are used. A built-in voltage regulator is provided to reduce the internal supply voltage to 4 V. Either *4 or *1 bit organization can be selected electrically, without pin connection changes. In the 0.55- mu m triple-polysilicon double-metal CMOS technology, the first polysilicon (polycide) is used for gate electrodes, the second (silicide) for the VSS lines of memory cells, and the third for resistive loads. The first metal is used for bit lines, and the second for the main word lines. The gate oxide thickness is 15 mm and the gate length is 0.55 mu m/0.65 mu m (NMOS/PMOS). The cell size is 3.4*5.6 mu m. The chip size is 7.7*18.6 mm.<<ETX>>

Noise Characteristics of Ion-Implanted Mos Transistors

Low‐frequency excess noise characteristics of ion‐implanted MOS transistors annealed above 1000u2009°C were investigated. Noise characteristics strongly depended on implant species, implant condition, and measurement conditions. In the case of implantation into opposite‐type conductivity substrates, such as 11B+‐implanted p‐channel or 31P+‐implanted n‐channel transistors, the equivalent input noise voltages measured at lower drain currents exhibited generation‐recombination (G‐R) noise caused by residual damage in the substrate. This noise component increased with increasing acceleration energy or implant dose. The G‐R noise decreased with increasing drain current. At higher drain currents the G‐R noise disappeared and the noise voltages of the implanted samples were somewhat smaller than that of the unimplanted samples. On the contrary, in the case of implantation into the same‐type conductivity substrate, such as 31P+‐implanted p‐channel or 11B+‐implanted n‐channel transistors, no G‐R noise component was ob...

Implant dose profile dependence of electrical characteristics of ion‐implanted MOS transistors

Ion‐implanted MOS transistors were fabricated and their electrical characteristics, such as threshold voltage, effective mobility, etc., were measured. In the 11B+‐implanted p‐channel case, threshold voltage VT can be shifted linearly with implant dose. These shifts ΔVT were entirely determined by the net dose entering silicon. On the other hand, in the 11B+‐implanted n‐channel case, threshold voltage shift ΔVT varied sublinearly with dose and showed strong dose profile dependence. The profiles were varied with changing implantation energies and annealing times. These results can be interpreted in accordance with the rapid decrease of the maximum surface depletion layer Xd max with the implant dose increase. Numerical calculations of threshold voltage shifts accounting for nonuniformly implanted profiles were compared with observed results. Good agreement was obtained. Effective mobilities μeff of 11B+‐implanted p ‐ and n ‐channel MOS transistors also showed different dose dependences. In the low‐dose reg...

A new full CMOS SRAM cell structure

A new full CMOS SRAM cell structure that can reduce the cell size to about a half of the conventional one, is presented. The cell structure is featured with such technologies as p/n polycide gate electrodes, shallow trench isolation, deep trench isolation and double level Al interconnects. Cell size measuring 7.4 × 14.1 µm (=104.34 µm2), has been achieved experimentally, which is about a half of the conventional one of the same design rule (1.2 µm). A test vehicle with a 4 Kb cell array was fabricated and its electrical characteristics were examined. Any appreciable degradations in the SRAM operation items were not observed. With this new cell structure, cell occupied area of 27.35 mm2is expected to be realized in 256 Kb full CMOS SRAM.

High speed 1 &#181;m CMOS technology

In order to pursue high speed performance of CMOS logic gates, 1µm CMOS technology has been realized by using advanced process technologies. CMOS logic gate arrays, with minimum feature size of 1.1µm, were prepared, and their operation speed performances were evaluated. Delay times per gate of 0.1 - 0.2 ns have been observed in CMOS logic arrays of 3NAND, 3NOR and F/O=3 INVERTER arrays, of 1.1µm design rule. To realize those logic arrays, 1µm double-well CMOS basic technology has been developed. In this paper, process technology, electrical characteristics of N-channel and P-channel transistors, and device operation characteristics of the CMOS logic arrays, are described.

A 64Kx1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.

A reduced size CMOS SRAM cell structure with two-level Al interconnection

A reduced size full CMOS SRAM cell structure having three Al wiring pitches, instead of conventional five Al wiring pitches, has been demonstrated experimentally by using an advanced two-level Al interconnect technology. A cell size measuring14.25 micro m times 18.9 micro m(=269microm2), which is at least less than 70% of the conventional five pitch cells size, has been realized. In order to investigate various technical issues relating to the CMOS SRAM with this new cell structure, a 1 Kb CMOS SRAM was fabricated, and its device operation characteristics were examined. Access time of less than 25 ns, and standby current of less than 1 nA, have been achieved with the SRAM. With this cell structure, cell area of 64 Kb CMOS SRAM has been estimated to be 17.7 mm2. Considerable speed improvement is also expected using this cell structure.

A 64K Dynamic MOS-RAM Using Short-Channel, Channel-Dope Technology

A 64K-bit dynamic MOS-RAM organized as 16K words × 4 bits has been realized by short channel, channel doping and single-level Si-gate technologies. This 64K-bit dynamic RAM has been fabricated successfully through only four photolithography processing steps. The RAM has been designed by using 2 µm design rules. For the short channel transistor, the effective channel length (Leff) is about 2 µm and the gate oxide thickness (tox) is 400A. As a result, the access time and the cycle time of the RAM are 110 ns and 300 ns, respectively. These values are 20 to 30 percent smaller than those of RAMs fabricated on highly impurity concentrated substrate. The power dissipation is about 150 mW at the cycle time of 400 ns and 15 mW at standby mode.

Erratum: Surface depletion region width dependence of threshold voltage shift of ion‐implanted MOS transistor

Even under the same implantation conditions, e.g., 50‐keV 11B+ ions implanted through 1100‐A gate oxides on 4‐Ω cm silicon substrates, the threshold voltage shift of n ‐channel MOS transistors is ∼55% of the shift of p ‐channel specimens, and deviation from linear dose dependence is observed for the n channel above a dose of 6×1011/cm2, while for a p ‐channel case the threshold voltage shift depends linearly on the net dose in silicon at least up to 1×1012/cm2. These results are discussed and explained with a calculated dose dependence that accounts for the large decrease of the maximum width of the depletion layer with increasing dose for acceptor‐implanted n ‐channel specimens.