Masahide Takada

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

With increase in the capacity of nonvolatile memories, the range of their use has been widening. A nonvolatile ferroelectric RAM (NVFRAM) based on a 1-transistor and 1-capacitor (1T/1C) memory cell has potential for fast-access time and small-chip size comparable with a DRAM. However, previously reported NVFRAMs are still slower than ordinary DRAMs, since driving a cell-plate line in NVFRAMs is slow. To avoid this, a non-driven cell plate line write/read scheme (NDP scheme) is presented which leads to NVFRAMs with as fast access time as DRAMs.

A BIST scheme using microprogram ROM for large capacity memories

A practical microprogram ROM BIST (built-in self-test) scheme suitable for LSI memories is proposed. This BIST can be used to install N-pattern and N/sup 2/-pattern test procedures, using BIST circuits with 12-word*10-b and 16-word*16-b ROMs, respectively. As a practical test procedure, a data retention test, in which BIST circuits with an 8-word*11-b ROM were used, was investigated. BIST circuit area overheads for the above three test patterns for 16-Mb DRAMs are less than 1%, 2%, and 1.5%, respectively. A testing method for the BIST circuits themselves, with no special BIST circuit overhead, is also proposed for more practical applications. The measured operational margin for a 16-Mb DRAM using the BIST showed a good agreement with that using an LSI tester.<<ETX>>

A 5 ns 1 Mb ECL BiCMOS SRAM

A 1 M-word*1-b emitter-coupled-logic (ECL) SRAM in 0.8- mu m BiCMOS technology that achieves 5-ns access time using (1) wired-OR predecoders, (2) ECL CMOS level converters with partial address decoding, and (3) sensing with small differential voltage swing on long read bus lines is described. The memory cell array is divided into two 512 K-cell subarrays. Each subarray consists of 16 32-kb arrays, each of which is organized into 256 rows and 128 columns. An X-decoder is located between a pair of 32-kb arrays. Address input signals are received by an ECL address buffer. The first circuit for address decoding is a wired-OR predecoder, which does the predecoding and predecoded signal line driving. Predecoded address signals with about 1.2-V voltage swing drive 16.5-mm predecoded lines between two 512-kb subarrays and are received by partial-decoding level converters at corresponding 32-kb arrays.<<ETX>>

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator

This 512 kw/spl times/8 b/spl times/4 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator, and a 0.4 /spl mu/m BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Circuit approaches include 1) zigzag double word-line, 2) centralized bit-line load layout, and 3) phase-locked-loop (PLL) with a multi-stage-tapped (MST) ring oscillator that generates not only a de-skewed internal clock, but also a clock-cycle-proportional pulse and a clock-edge-lookahead pulse. >

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55- mu m CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm/sup 2/ chip area was attained by implementing 4.05- mu m/sup 2/ storage cells. The installed ROM was composed of 18 words*10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm/sup 2/ and the area overhead is about 1%, it proves to be promising for large-scale DRAMs. >

A 300-MHz 16-b BiCMOS video signal processor

A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5- mu m BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5*17.0-mm/sup 2/ die area. >

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word*1 b/1 M word*4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm*8.77 mm. Memory cell size is 5.8 mu m*3.2 mu m. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55- mu m BiCMOS process technology with a triple-well structure. >

High speed submicron BiCMOS memory

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAMs with 0.8 /spl mu/m, 0.55 /spl mu/m and 0.4 /spl mu/m design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAMs. Future prospects for submicron BiCMOS memories are also forecasted. >