Toshio Wada

A read-only memory using MAS transistors

A nonvolatile read-only memory using MAS (metal-alumina-silicon) transistors, that is electrically writable, is expected to hold written data for 1019hrs., and is resettable by radiation, such as x-rays and electron beams without damage, will be described.

MAS-ROM-electrically reprogrammable ROM with decoder

The electrical characteristics of an MAS-ROM with on-the-chip X-Y matrix decoding and its reliabilities are evaluated. The MOS-ROM makes use of the so-called charge-storage phenomena in the gate insulator film and provides an electrical reprogrammable and nonvolatile integrated-circuit memory device in which one memory cell is composed only of an N-channel enhancement-type MAS transistor. The threshold voltage of the transistor is selectively increased by electron injection from the channel and decreased by the application of high negative voltage to the gate. The reliability test shows that the long-term decay has a logarithmic dependence on time with a slope of 0.7 V per decade of storage time under a gate voltage of +10 V at 150/spl deg/C.

Electrical Characteristics of Metal Al2O3–SiO2–Si (MAOS) Transistors

The dependence of effective mobility and the threshold voltage of metal-aluminum oxide-silicon oxide-silicon (MAOS) transistors upon the thickness of silicon oxide (SiO2) and upon the ambient gas of heat treatment was examined. The effective mobility of MAOS transistors, whose gate insulator film consists of a double layer of Al2O3 (about 1500A) and SiO2 (20~110A), is 40~460 cm2/Vsec depending upon the thickness of SiO2 and this value is small compared with 640 cm2/Vsec of MOS structure. However it increases up to 300~650 cm2/Vsec after the heat treatment in hydrogen at 500°C for 4 hours. The small effective mobility of as-grown sample is caused by a large number of surface states near the conduction band edge. These surface states are likely related to a kind of acceptor type defects.

A 16-DIP 64Kb static MOS RAM

A 64K×1b fully static MOS RAM using 1.5μm design rules will be described. The device has multiplexed addressing and is assembled in a standard 300-mil 16-pin DIP.

A 64K Dynamic MOS-RAM Using Short-Channel, Channel-Dope Technology

A 64K-bit dynamic MOS-RAM organized as 16K words × 4 bits has been realized by short channel, channel doping and single-level Si-gate technologies. This 64K-bit dynamic RAM has been fabricated successfully through only four photolithography processing steps. The RAM has been designed by using 2 µm design rules. For the short channel transistor, the effective channel length (Leff) is about 2 µm and the gate oxide thickness (tox) is 400A. As a result, the access time and the cycle time of the RAM are 110 ns and 300 ns, respectively. These values are 20 to 30 percent smaller than those of RAMs fabricated on highly impurity concentrated substrate. The power dissipation is about 150 mW at the cycle time of 400 ns and 15 mW at standby mode.