Osamu Tomisawa

A 600 MHz single-chip multiprocessor with 4.8 GB/s internal shared pipelined bus and 512 kB internal memory

This 600 MHz single-chip multiprocessor consists of two M32R 32 b CPU cores and 512 kB shared SRAM and is designed for embedded systems. Embedded processors are required with increased performance while power dissipation is paramount for battery-operated applications. The design is implemented in a single-chip in a 0.15 /spl mu/m 4M CMOS process and operates at 600 MHz with 800 mW peak power dissipation.

A 50 MHz 24 b floating-point DSP

A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.<<ETX>>

A Hierarchical Standard Cell Approach for Custom VLSI Design

A custom VLSI design technique, using an integrated CAD system is described. The design system features on the hierarchical design process and layout design capability by system designers (customers). As for application, high-performance LSIs for 16-bit CPU were developed. The LSI design was accomplished in a short period (three months with three designers) due to the hierarchical standard cell approach. The LSI chip contains about 20 K transistors in an 8.84 mm X 8.88 mm die area. High-speed operation (machine cycle = 200 ns) and a high density of 291 transistors/mm2 were obtained with low power consumption (1.2 W) owing to the mixed-MOS type standard cell library and this approach.