Takeshi Tokuda

A built-in self-test for ADC and DAC in a single-chip speech CODEC

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The performance characteristics of the ADC and the DAC designed in according with the CCITT recommendations are measured using BIST. Three characteristics have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response. Therefore, test-time is reduced, analog or mixed-signal test equipment is not needed, and finally, test-cost is reduced compared with conventional test methods. This paper describes the BIST design and evaluational results.<<ETX>>

Fuzzy inference and fuzzy inference processor

Fuzzy inference, a data processing method based on the fuzzy theory that has found wide use in the control field, is reviewed. Consumer electronics, which accounts for most current applications of this concept, does not require very high speeds. Although software running on a conventional microprocessor can perform these inferences, high-speed control applications require much greater speeds. A fuzzy inference date processor that operates at 200000 fuzzy logic inferences per second and features 12-b input and 16-b output resolution is described.<<ETX>>

A 100-mega-access per second matching memory for a data-driven microprocessor

A high-throughput matching memory (MM) for a data-driven microprocessor is discussed. An MM can be constructed using a hashing memory. However, one of the biggest problems with hashing memory is the necessity for selective processing whenever hashed address conflicts occur. To eliminate this problem, the MM incorporated a small amount of associative memory (32 words*50 b) as well as the hashing memory (512 words*42 b). The matching operation is subdivided into three pipeline stages, all controlled by the elastic pipeline scheme. With this structure, an MM with a high throughput of 100-mega-access/s MM can be realized. >

A 12 b resolution 200 kFLIPS fuzzy inference processor

A fuzzy inference processor that performs fuzzy inference with 12-b resolution input at 200 kFLIPS (fuzzy logical inferences per second) is described. Three techniques are adopted to attain this performance: (1) membership-function generators constructed of combinational logic, which calculate a membership-function value in less than half of a clock cycle; (2) rule instructions that execute one-rule-by-one instruction in an antecedent unit; and (3) an improved add/divide algorithm that calculates a centroid in a consequent unit. The block diagram of this processor is shown. The chip, fabricated by 1- mu m single-polycide, double-metal CMOS technology, contains 86-k transistors in a 7.5-mm*6.7-mm die, and is packaged in an 80-pin flat package. The chip operates at more than 20-MHz clock frequency at 5 V.<<ETX>>

A 1.8 V 36 mW DSP for the half-rate speech codec

A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.

A 50 MHz 24 b floating-point DSP

A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.<<ETX>>

A data-driven architecture for distributed parallel processing

A single-chip data-driven microprocessor with special functions for distributed parallel processing is described. The implemented functions necessary for parallel processing are: relative addressing mode for program memory; efficient test and set operation of arbitrary data in data memory; transparent access of distributed shared memory; and dynamic load distribution among multiprocessors. With this microprocessor, practical parallel processing systems which exploit a wide area of scientific applications can be constructed.<<ETX>>