Takio Ohno

An elastic pipeline mechanism by self-timed circuits

An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors. >

A 400 K-transistor CMOS sea-of-gates array with continuous track allocation

A 0.8- mu m CMOS sea-of-gates (SOG) array with first-level wiring channels perpendicular to transistor rows and 40 0K transistors is integrated on a 6*7-mm/sup 2/ chip. Implementation of a 64-bit multiplier shows 60-percent gate utilization and density of 1410 G/mm/sup 2/. The wiring length of the multiplier is 70 percent of that in a conventional SOG. >

A 100-mega-access per second matching memory for a data-driven microprocessor

A high-throughput matching memory (MM) for a data-driven microprocessor is discussed. An MM can be constructed using a hashing memory. However, one of the biggest problems with hashing memory is the necessity for selective processing whenever hashed address conflicts occur. To eliminate this problem, the MM incorporated a small amount of associative memory (32 words*50 b) as well as the hashing memory (512 words*42 b). The matching operation is subdivided into three pipeline stages, all controlled by the elastic pipeline scheme. With this structure, an MM with a high throughput of 100-mega-access/s MM can be realized. >

A 12 b resolution 200 kFLIPS fuzzy inference processor

A fuzzy inference processor that performs fuzzy inference with 12-b resolution input at 200 kFLIPS (fuzzy logical inferences per second) is described. Three techniques are adopted to attain this performance: (1) membership-function generators constructed of combinational logic, which calculate a membership-function value in less than half of a clock cycle; (2) rule instructions that execute one-rule-by-one instruction in an antecedent unit; and (3) an improved add/divide algorithm that calculates a centroid in a consequent unit. The block diagram of this processor is shown. The chip, fabricated by 1- mu m single-polycide, double-metal CMOS technology, contains 86-k transistors in a 7.5-mm*6.7-mm die, and is packaged in an 80-pin flat package. The chip operates at more than 20-MHz clock frequency at 5 V.<<ETX>>

A 40 MFLOPS 32-bit floating-point processor

A 40 MFLOPS (million floating-point operations per second), 32-bit floating-point processor (FP) for a single-board data-driven processor is developed using a pipeline configuration called the elastic pipeline structure. Because there is no need to add controls for pipeline flushing by virtue of the data-driven processing principle, it is possible to employ extensively subdivided pipeline stages. The elastic mode of data transfer between pipeline stages and distributed execution controls along the pipeline result in minimum deterioration of the inherent logic switching speed. The structure of the FP is shown together with details of the ALU (arithmetic logic unit) block. The fabrication process and chip specifications are summarized.<<ETX>>

A CMOS sea-of-gates array with continuous track allocation

A macrocell architecture which is suitable for sea-of-gates (SOG) arrays and improves gate density is described. A layout scheme using a novel structure called column macrocell (CMC) implements every macrocell by stacking BCs (basic cells) along the BC column until enough gates are accumulated. In the CMC structure, the first-level wiring runs along the BC column, and the wiring channel width can be adjusted by 1-2 tracks. Therefore just as many tracks as are necessary in a channel are produced by first-level wiring. The effectiveness of the CMC structure is verified by implementing an SOG chip using LDD (lightly doped drain) PMOS and NMOS transistors with 0.8- mu m physical and 0.55- mu m effective gate length. The features of the CMC structure are compared with those of the RMC (row macrocell) structure.<<ETX>>

A 50 MHz 24 b floating-point DSP

A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.<<ETX>>

VLSI implementation of a variable-length pipeline scheme for data-driven processors

A VLSI-oriented variable-length pipeline structure for data-driven processors is presented. Ordinary inline pipelines have the problem of minimizing the average total processing time through the pipeline, since subdivision of a function along the pipeline is usually optimized for the most complex operations in spite of the fact that simpler operations need fewer stages. As a solution to this problem, a variable-length pipeline scheme in which data go through only the necessary stages according to information contained within is proposed. The scheme has been implemented on a test chip to verify performance. The chip demonstrated a minimum fall-through time (data transmission time from input to output) of 14.4 ns and a data transmission rate in the pipeline of 59 megaword/s (that is, 1/16.9 ns) as a first-in first-out (FIFO) store. By modifying the data transfer control and allocating the processing functions corresponding to the data interval of 16.9 ns, this scheme is applicable as a high-performance processing unit for data-driven processors. >