P.A. Mawby

Physically based compact device models for circuit modelling applications

Abstract Physically based compact device models of the MOSFET, as well as PiN diode and insulated gate bipolar transistor (IGBT) are presented in this paper. For the correct description of static and dynamic behaviour of power bipolar devices (IGBT and PiN diode) a 1D module for the drift zone (low doped n-base region) is presented that incorporates conductivity modulation and non-quasistatic charge storage effect. Finally, it is possible to transform, relatively easily, these electric models into the electrothermal models by adding an extra node (thermal node) to the electrical compact models. This thermal node will store information about junction temperature of the active device and it represents a connection between the device and rest of the circuit thermal network.

Dynamic electro-thermal physically based compact models of the power devices for device and circuit simulations

New dynamic electro-thermal models of the power MOSFET, and power bipolar devices (PiN diode and IGBT) are presented in this paper. Firstly, electric device models were made, and then they were transformed into the electro-thermal models by adding a thermal node. This thermal node stores information about junction temperature and represents a connection between the device and rest of the circuit thermal network. All models have been found to be efficient and robust in all cases examined.

Highly effective junction isolation structures for PICs based on standard CMOS Process

This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-/spl mu/m CMOS technology.

Numerical analysis of a trench VDMOST structure with no quasi-saturation

Abstract This paper presents a modification to the conventional VDMOS transistor which considerably reduces the effect of quasi-saturation. This modification consists of introducing a deep trench into the structure which is located in the centre of each MOS cell. By extending the gate oxide and metalization into the trench, an accumulation layer is formed deep into the bulk of the device, which modulates the total drift region resistance. A two-dimensional numerical simulator is used to investigate the electrical and thermal performance of the device through which it is shown that the device not only removes the quasi-saturation effect, but also gives lower on-resistance, and much more attractive synchronous rectifying characteristics when compared to the conventional VDMOST structure with an equivalent geometry.

Numerical modelling of stress-induced failure in sub-micron aluminium interconnects in VLSI systems

Abstract Stress-induced failure is investigated based on numerical modelling of the diffusional relaxation and groove growth in an aluminium line. A numerical model, based on surface and grain boundary diffusion, is improved and made to be very useful for time to failure estimation.

Design of IGBTs for latch-up free operation

Abstract An N-type buffer region is introduced into the N+ source of the IGBT to make it latch-up free. This is done by controlling the resistances of the buffer N region and the P base. A latch-up free condition based on these resistances is presented. 2D numerical simulation is used to demonstrate the concept and the results show that the device can be made to be latch-up free by decreasing the doping concentration of the N-buffer or increasing the doping in the P base in accordance with this condition. Further, a control gate is introduced into the buffer layer to control its resistance, and the simulation results show that latch-up can also be eliminated by applying a sufficiently negative voltage on this gate. Lastly, the effect of the MOS gating level on the latch-up for IGBT is given, and the results are discussed qualitatively.