P. Igic

Dynamic electro-thermal physically based compact models of the power devices for device and circuit simulations

New dynamic electro-thermal models of the power MOSFET, and power bipolar devices (PiN diode and IGBT) are presented in this paper. Firstly, electric device models were made, and then they were transformed into the electro-thermal models by adding a thermal node. This thermal node stores information about junction temperature and represents a connection between the device and rest of the circuit thermal network. All models have been found to be efficient and robust in all cases examined.

Technology for Power Integrated Circuits with Multiple Vertical Power Devices

An original work in developing technology that allows the integration of multiple vertical power devices within power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability

Silicon carbide Schottky diodes and MOSFETs: Solutions to performance problems

Silicon carbide has long been hailed as the successor to silicon in many power electronics applications. Its superior electrical and thermal properties have delivered devices that operate at higher voltages, higher temperatures and with lower on-resistances than silicon devices. However, SiC Schottky diodes are still the only devices commercially available today. Though SiC Schottkys are now being used with silicon IGBTs in dasiahybridpsila inverter modules, the real advantages will be seen when silicon switching devices can be replaced by SiC. This paper describes the current state of SiC diode and MOSFET technology, discussing possible solutions to making these devices commercially viable.

Highly effective junction isolation structures for PICs based on standard CMOS Process

This paper presents novel and highly effective junction isolation structures for power integrated circuits. The negative feedback-activated junction isolation is presented and it is proven to be very effective in blocking substrate current from reaching the logic circuitry (orders of magnitude more effective than standard junction isolation techniques). Additionally, in an attempt to further improve the blocking capabilities of junction isolations the use of multiple or combined structures is investigated whilst keeping the surface area used for isolation device in the same range as for the single structures. All isolation structures presented here are based on a 0.6-/spl mu/m CMOS technology.

Thermal model of power semiconductor devices for electro-thermal circuit simulations

An electro-thermal (ET) strategy used for ET circuit simulations is described in this paper. An original program for a MATLAB environment based on a deconvolution method is written and used for a determination of the RC dynamic thermal network parameters. An excellent agreement is obtained between experimental thermal transient response function of the device for a step function excitation and simulated one obtained using corresponding RC thermal network.

Simulation of current collapse in the 0.25 µm gate Length Al 0.28 Ga 0.72 N/GaN HEMT

A 2D drift-diffusion (DD) and Hydrodynamic (HD) transport models within ATLAS simulation toolbox by Silvaco have been calibrated against experimental I-V characteristics of the 0.25μm gate length GaN High Electron Mobility Transistor (HEMT). The simulations take into account both piezoelectric and spontaneous polarization effects at the interface of AlGaN and GaN. The simulations have been employed to investigate the current collapse phenomenon that plays a key role in the output characteristics of a device which can significantly limit the output power. The current collapse is investigated using shallow acceptor traps in the both AlGaN and GaN layers.

Perspective on Power IC technology: From design lab to wafer fab

A case study regarding development of a 100V Power IC technology is presented in this paper. A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon. Different electrical isolation schemes have also been investigated.

Active junction isolation for smart power integrated circuits

A structure for the isolation of power transistors from (CMOS) control circuitry used in smart power integrated circuits is proposed. This negative feedback activated junction isolation is compatible with standard CMOS technology.

Investigation of the thermal stress field in a multilevel aluminium metallization in VLSI systems using finite element modelling approach

The impact of a titanium barrier layer on the residual thermal stress in passivated multilevel aluminium metallization structure (Al lines and connecting via) is investigated using an advanced finite element approach. It is confirmed that the titanium, when is presented in the structure, can significantly improve the reliability of the Al metallization.

Scaling and traps induced degradation of cutoff frequency in GaN HEMT

The effects of electric field induced traps generation in the drain access region is studied using industry standard TCAD, Atlas by Silvaco [1]. We show that the reduction in the cut-off frequency of the device from 13.9 (GHz) to 11.25 (GHz) could be linked to the electric field induced traps. We have used acceptor traps at an energy level of ET = Ev + 0.9 (eV), corresponding to substitutional carbon in GaN, and a concentration of NIT = 5 ×1017(cm-3) to model the induced traps. Although vertical scaling has been used to reduce short channel effects, we observe that this leads to a reduction in the current arising from the reduced ionised surface donors [2].