S. Batcup

Investigation of the power dissipation during IGBT turn-off using a new physics-based IGBT compact model

Abstract New compact models of the IGBTs (both non-punch through IGBT (NPTIGBT) and punch-through IGBT (PTIGBT)) are presented in this paper. The models are implemented in the SABER circuit simulator and used for a study of IGBT anode current and voltage characteristics during a device turn-off (clamped inductive load circuit with gate controlled turn-off), since these parts of the transient characteristics essentially predict the power dissipation ( V × I ) inside the device. It is shown that PTIGBTs are faster than NPTIGBTs, this becoming more apparent at higher clamp voltages.

Technology for Power Integrated Circuits with Multiple Vertical Power Devices

An original work in developing technology that allows the integration of multiple vertical power devices within power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability

Thermal model of power semiconductor devices for electro-thermal circuit simulations

An electro-thermal (ET) strategy used for ET circuit simulations is described in this paper. An original program for a MATLAB environment based on a deconvolution method is written and used for a determination of the RC dynamic thermal network parameters. An excellent agreement is obtained between experimental thermal transient response function of the device for a step function excitation and simulated one obtained using corresponding RC thermal network.

A lateral double-diffused magnetic sensitive metal-oxide-semiconductor field-effect transistor with integrated n-type Hall plate

A magnetic sensitive device, lateral double-diffused magnetic sensitive metal-oxide-semiconductor field-effect transistor (LD MagFET), combining the sensory operation of conventional magnetic sensitive metal-oxide-semiconductor field-effect transistors (MagFETs) and Hall plates is proposed. The sensor device is fully compatible with a high-voltage complementary metal-oxide-semiconductor (CMOS) technology. It is found that the LD MagFET with integrated Hall plate exhibits an order of magnitude higher relative magnetic sensitivity in comparison with the split-drain silicon MagFETs in standard CMOS.

An advanced physics-based sub-circuit model of a punch-trough insulated gate bipolar transistor

An advanced sub-circuit model of the punch-trough insulated gate bipolar transistor (PT IGBT) based on the physics of internal device operation has been described in this article. The one-dimensional physical model of low-gain wide-base BJT is employed based on the equivalent non-linear lossy transmission line, whereas a SPICE Level 3 model is used for the diffused MOST part. The influence of voltage dependent drain-to-gate overlapping capacitance and the conductivity modulated base (drain) ohmic resistance are modelled separately. The main advantages of novel PT IGBT model are a small set of model parameters, an easy implementation in SPICE simulator and the high accuracy confirmed by comparing the simulation results with the electrical measurements of test power circuit.

An Advance Physics-Based Sub-Circuit Model of IGBT

An advanced physics-based equivalent-circuit model of IGBT has been described featuring a high accuracy in predicting device electrical performance in real circuit applications. A SPICE Level 3 model is employed for simulation of the equivalent DMOSFET, while the voltage dependant drain- to-gate overlapping capacitance and drain ohmic resistance elements are modelled separately. The one-dimensional physics- based model of the low-gain BJT device is developed using the equivalent non-linear lossy transmission line sub-circuit. IGBT model is implemented in PSPICE circuit simulator and high accuracy of the model is demonstrated by comparing the simulation results with the electrical measurements of several test power circuits.

Characterization of MOS interfaces on protected and un-protected 4H-SiC surfaces

In this paper, we present investigations performed on 4H-SiC surfaces annealed at high temperature in the presence of a protective carbon cap and compare these to samples fabricated by the same process, but without a protective layer. The high temperature treatment resulted in sample surfaces with various roughnesses. The annealed samples have been oxidised to fabricate MOS structures in order to investigate the effect of annealing on the physical properties SiO2/SiC interfaces. Structures have been characterized using C-V measurements. Results suggest that treatments to reduce surface roughness caused by annealing, prior to any oxidation, are effective in reducing the density of interface traps. The density of SiO2/SiC interface traps for samples treated prior to oxidation is lower than interface trap densities for annealed samples with no preoxidation roughness reduction treatment.

A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture

A study of the latch-up robustness for a new power IC technology involving Si substrate/wafer modifications is presented in this paper. The results shown confirm that for dual-well CMOS technologies, changes in the substrate/epitaxial layer structure are a satisfactory way of improving power IC process capabilities without compromising the CMOS performance. Both simulation and experimental results are presented.

Dynamic Thermal Simulation of Power Devices Operating with PWM Signals

Fast power devices thermal simulation method based on averaging power losses over each cycle of PWM switching frequency is presented in this paper. For implementing a long real time dynamic thermal simulation of power devices, device power losses during transient process and static characteristics are defined as a function of device conduction current and junction temperature, and are represented by a lookup table. By carrying out the circuit electrical simulation, the device conduction current can be obtained. By combining the device conduction currents, global device temperature (GDT) and the data from the lookup table, the average power loss over each cycle of PWM switching frequency is then calculated for carrying out the thermal simulation. With the proposed method, a relative large simulation time step can be employed and simulation speed can be increased dramatically. The method is suitable for a long real time thermal simulation for complex power electronics systems