T. Uchino

Metal catalyst-free low-temperature carbon nanotube growth on SiGe islands

A metal-catalyst-free growth method of carbon nanotubes (CNTs) has been developed using chemical vapor deposition of CNTs on carbon-implanted SiGe islands on Si substrates. From scanning electron microscopy and Raman measurements, the fabricated CNTs are identified as single-walled CNTs with a diameter ranging from 1.2 to 1.6 nm. Essential parts of the substrate preparation after CVD SiGe growth and carbon implant are a chemical oxidization by hydrogen peroxide solution and a heat treatment at 1000 °C prior to CNT growth. We believe that these processes enhance surface decomposition and assist the formation of carbon clusters, which play a role in seeding CNT growth. The growth technique is a practical method of growing metal-free CNTs for a variety of applications, while at the same time opening up the prospect of merging CNT devices into silicon very-large-scale-integration technology.

Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200/spl deg/C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100> wafer surface.

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at VDS=1 V) and a drain-induced barrier lowering of 0.12 V

Growth of Single-Walled Carbon Nanotubes Using Germanium Nanocrystals Formed by Implantation

This paper presents a complementary metal oxide semiconductor compatible method for the chemical vapor deposition of singlewalled carbon nanotubes. The method uses Ge implantation into a SiO2 layer to create Ge nanocrystals, which are then used to produce SWNTs. The results of atomic force microscopy and scanning electron microscopy analyses indicate that Ge implantation provides good control of particle size and delivers a well-controlled SWNT growth process. The SWNT area density of 4.1 +- 1.2 um in length/um2 obtained from the Ge nanocrystals is comparable to that obtained from metal-catalyst-based methods used to fabricate SWNT field-effect transistors. A carbon implantation after Ge nanocrystal formation significantly enhances the process operating window for the growth of the SWNTs and increases the area density.

On the mechanism of carbon nanotube formation: the role of the catalyst.

This work examines the recent developments in non-traditional catalyst-assisted chemical vapour deposition of carbon nanotubes (CNTs) with a view to determining the essential role of the catalyst in nanotube growth. A brief overview of the techniques reliant on the structural reorganization of carbon to form CNTs is provided. Additionally, CNT synthesis methods based upon ceramic, noble metal, and semiconducting nanoparticle catalysts are presented. Experimental evidence is provided for CNT growth using noble metal and semiconducting nanoparticle catalysts. A model for CNT growth consistent with the experimental results is proposed, in which the structural reorganization of carbon to form CNTs is paramount.

Anisotropic upper critical fields of orthorhombic single phase YBa2Cu3O7−δ studied using preferentially oriented pellets

Anisotropic behavior of the upper critical fields Hc2 studied in as-sintered disk of YBa2Cu3O7-δ and the characterization of the samples by X-ray diffraction analysis are described. Highly oriented samples with c-axis perpendicular to the disk plane show anisotropic behavior of Hc2 for midpoints and isotropic behavior for the offset field Hc2off defined at 1 % points: the slope (-dHc2/dT) for midpoints is 3.8 T/K and 2.6 T/K for the magnetic field parallel and perpendicular to the disk plane, respectively, and the offset field is about 5-6 T at 80 K. An analysis based on a simplified model suggests the anisotropy factor e of about 0.2 for YBa2Cu3O7-δ. The X-ray powder diffraction combined with Rietveld analysis together with the resistivity measurement show the samples to be single phase with orthorhombic structure and 90 Krange Tc.

Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10nm. For pillar thicknesses between 200-60nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias V/sub dc/ for which the increased drain-current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60-10nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate-gate coupling contribute to the drain-current for pillar thicknesses between 100-40nm.

Catalyst free low temperature direct growth of carbon nanotubes

A metal catalyst free direct growth process has been developed for the CVD of carbon nanotubes (CNTs) on carbon implanted SiGe islands or Ge dots on Si substrates. From TEM and Raman measurements, the fabricated CNTs are identified as single-walled CNTs (SWNTs) with diameter ranging from 1.2 to 2.1 nm. Essential parts of the substrate preparation after SiGe or Ge dot growth and carbon ion implantation are a chemical oxidation and preheating at 1000/spl deg/C prior to CNT growth. We believe that the lower melting point of Ge and oxidation enhanced surface decomposition assist the formation of carbon clusters.

Superconductivity Transition of High-Tc Y–Ba–Cu–O Systems with Multi- and Single-Phase; Tc and Hc2

Superconducting transition in the magnetic field up to 9T and the upper critical field Hc2 near Tc were investigated for Y1Ba2Cu3O7-δ with orthorhombic single phase, comparing with the Y–Ba–Cu–O samples with multi-phase. The upper critical field Hc2 is very large for single phase sample; the offset field Hc2off defined at 1% point is about 10T even at 76K and the slope (-dHc2/dT) for mid-point is 3.8T/K.