M. M. A. Hakim

Thin film polycrystalline silicon nanowire biosensors.

Polysilicon nanowire biosensors have been fabricated using a top-down process and were used to determine the binding constant of two inflammatory biomarkers. A very low cost nanofabrication process was developed, based on simple and mature photolithography, thin film technology, and plasma etching, enabling an easy route to mass manufacture. Antibody-functionalized nanowire sensors were used to detect the proteins interleukin-8 (IL-8) and tumor necrosis factor-alpha (TNF-α) over a wide range of concentrations, demonstrating excellent sensitivity and selectivity, exemplified by a detection sensitivity of 10 fM in the presence of a 100,000-fold excess of a nontarget protein. Nanowire titration curves gave antibody-antigen dissociation constants in good agreement with low-salt enzyme-linked immunosorbent assays (ELISAs). This fabrication process produces high-quality nanowires that are suitable for low-cost mass production, providing a realistic route to the realization of disposable nanoelectronic point-of-care (PoC) devices.

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200/spl deg/C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100> wafer surface.

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at VDS=1 V) and a drain-induced barrier lowering of 0.12 V

Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs

Direct tunneling gate current in MOS structures with ultra-thin gate-oxides in the presence of inelastic scattering in oxide region is studied using a new technique. Numerically calculated results for nMOS devices show that due to inelastic scattering, gate current increases in devices with oxide thickness equal to 2 nm or higher. Inelastic scattering effects are more pronounced at lower gate voltages. However, when the oxide thickness is reduced below 2 nm, inelastic scattering has no significant effect on gate current.

Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10nm. For pillar thicknesses between 200-60nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias V/sub dc/ for which the increased drain-current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60-10nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate-gate coupling contribute to the drain-current for pillar thicknesses between 100-40nm.

A self-aligned silicidation technology for surround-gate vertical MOSFETS

We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120 nm n-channel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DIBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DIBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78 mV/decade and a DIBL of 30 mV/V. For an 80 nm channel length, a 43% improvement in the drive current is obtained.

Computationally efficient quantum-mechanical technique to calculate direct tunnelling gate leakage current in metal-oxide-semiconductor structures

We propose a computationally efficient, accurate and numerically stable quantum- mechanical technique to calculate the direct tunneling (DT)gate current in metal-oxide-semiconductor (MOS) structures. Knowledge of the imaginary part G of the complex eigenenergy of the quasi-bound inversion layer states is required to estimate the lifetimes of these states. Exploiting the numerically obtained exponential dependence of G on the thickness of the gate-dielectric layer even in the sub-1-nm-thickness regime, we have simplified the determination of G in devices where it is too small to be calculated directly. It is also shown that the MOS electrostatics, calculated self-consistently with open boundary conditions, is independent of the dielectric layer tickness provided that the other parameters remain unchanged. Utilizing these findings, a computationally efficient and numerically stable method is developed for calculating the tunneling current–gate voltage characteristics. The validity of the proposed model is demonstrated by comparing simulation results with experimental data. Sample calculations for MOS transistors with high-K gate-dielectric materials are also presented. This model is particularly suitable for DT current calculation in devices with thicker gate dielectrics and in device or process characterization from the tunneling current measurement.

Self-Aligned Silicidation of Surround Gate Vertical MOSFETs for Low Cost RF Applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A source-drain (S/D) activation anneal of 30 s at 1100°C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μm lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar.

Increased Lateral Crystallization Width during Nickel Induced Lateral Crystallization of Amorphous Silicon Using Fluorine Implantation

This paper reports a study of the effect of fluorine implantation on the nickel-induced lateral crystallization of amorphous silicon. To distinguish the effects of the fluorine and the implantation damage, the fluorine implant is either made directly into the a-Si or into the buffer oxide below the a-Si. For a 20 h anneal at 500°C, both types of fluorine implant give a 65% increase in the lateral crystallization width, a five times reduction in the density of nickel silicide precipitates, and an improved grain texture. In contrast, for 20 h anneals at 550 and 600°C, both types of fluorine implant give 29% and 85% reductions in the lateral crystallization width, respectively. The identical results obtained for fluorine implantation into the a-Si and the buffer oxide indicates that the effects observed are due to chemical effects of the fluorine rather than implantation damage in the a-Si. The increased crystallization width at 500°C is explained by the suppression of random crystallization at the bottom a-Si/SiO2 interface. The reduced crystallization widths at 550 and 600°C are attributed to the diffusion and activation of fluorine and the formation of Si–F bonds making the a-Si more resistant to silicide-mediated phase transformation.

Improved sub-threshold slope in RF vertical MOSFETS using a frame gate architecture

We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects when the channel length is scaled, while control devices show significantly degraded sub-threshold slope and DIBL. The frame gate vertical MOSFETs show near ideal sub-threshold slopes of 70-80 mV/decade and DIBL of 30-35 mV/V in a 100 nm gate length nMOS device. In contrast, the control vertical MOSFETs without the frame gate exhibit sub-threshold slopes of 110 to 140 mV/decade and DIBL of 100 to 280 mV/V. This improved sub-threshold slope is explained by the elimination of etch damage during gate etch.