P. Baltus

An 8-bit 100-MHz full-Nyquist analog-to-digital converter

An 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The converter is implemented in an oxide-isolated bipolar process, requiring 800 mW from a single 5.2-V supply. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation. >

Substrate transfer for RF technologies

The constant pressure on performance improvement in RF processes is aimed at higher frequencies, less power consumption, and a higher integration level of high quality passives with digital active devices. Although excellent for the fabrication of active devices, it is the silicon substrate as a carrier that is blocking breakthroughs. Since all devices on a silicon wafer have a capacitive coupling to the resistive substrate, this results in a dissipation of RF energy, poor quality passives, cross-talk, and injection of thermal noise. We have developed a low-cost wafer-scale post-processing technology for transferring circuits, fabricated with standard IC processing, to an alternative substrate, e.g., glass. This technique comprises the gluing of a fully processed wafer, top down, to an alternative carrier followed by either partial or complete removal of the original silicon substrate. This effectively removes the drawbacks of silicon as a circuit carrier and enables the integration of high-quality passive components and eliminates cross-talk between circuit parts. A considerable development effort has brought this technology to a production-ready level of maturity. Batch-to-batch production equipment is now available and the technology and know-how are being licensed. In this paper, we present four examples to demonstrate the versatility of substrate transfer for RF applications.

Optimizing RF front ends for low power

This paper discusses optimizations for the power dissipation of RF front ends in portable wireless devices. A breakthrough in power dissipation can be achieved by simultaneously optimizing the antenna interface, circuits, and IC technology of such devices. A model that predicts the minimum power dissipation of a front end for both short-range and long-range connections will be introduced. Using these models, the impact of the antenna interface on the power dissipation will be assessed. Using two antennas with equal gain combining, a typical power dissipation reduction of 2.5 to 30 times can be achieved. Using high-impedance circuits for short-range systems in combination with silicon-on-anything technology, a further reduction of power dissipation by up to one order of magnitude can be realized.

DECT Zero IF Receiver Front End

A fully integrated zero IF receiver front end for Digital European Cordless Telecommunications (DECT) has been designed and implemented in an advanced BiCMOS process. The performance of this receiver is competitive with a superheterodyne receiver.

EXIST: an interactive VLSI architectural environment

EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOORIST) and a database (DATABIST). EXIST contains several unique features including: editing while in simulation, manual and automated hierarchical floorplan optimization, and user-friendly interface based on the model-view controller paradigm of Smalltalk. These features make EXIST a promising environment for exploration of alternative VLSI architectures, such as RISC (reduced instruction-set computer) controllers.<<ETX>>

Impact of GHz disturbances on DC parametric measurements

RF signals from mobile phones or WLAN transmitters can affect DC parametric measurements. A transistor test structure inside a wafer prober can behave as a GHz receiver when the needles or the manipulators that probe these transistors pick up sufficiently strong GHz signals. This paper shows examples of such occurrences and presents a technique for assessing the vulnerability of parametric measurement systems for GHz signals.

An efficient multi-level multi-wire differential interface

The authors introduce a multilevel, multiwire interface that, while retaining the differential properties of the signal, can transmit information at higher rates than would be possible through a binary differential interface with the same number of wires. Besides being rather insensitive to external electromagnetic noise sources, such an interface generates very little electromagnetic radiation. An efficient implementation of this interface, which adds very little complexity or die area over binary designs, has been designed and is currently being fabricated. Interfaces of this type can be used in designs which need a differential interface, but which would otherwise be limited by the number of pins on an IC package.<<ETX>>

Put you power into SOA LNAs

Low noise amplifiers are ultimately limited in performance and power dissipation by parasitics introduced by the IC process. The important parasitics can be determined by investigating the tradeoffs between power, performance and the performance limits of simple building blocks. Most of these parasitics are related to the silicon substrate. Silicon-On-Anything is an IC technology in which the substrate is completely substituted by another material. The technology also includes an NPN device optimized specifically for low power RF. By adapting the LNA design methods, a reduction in power dissipation by one order of magnitude has already been demonstrated. Directions for further improvements are indicated.

A high speed BiCMOS table look-up gate

The authors describe a BiCMOS programmable gate array (PGA) with subnanosecond logic block delay and low power consumption. Each logic block can implement any Boolean function of three inputs, a D-latch, or an SR-latch. The PGA is supported by an advanced design environment, which includes schematic capture, interactive functional simulation, logic minimization, and technology mapping.<<ETX>>

AEDAM: design of high performance multi-process systems

AEDAM (Architecture Exploration and Design system for Application-specific Multiprocesses) is a research project investigating methods to achieve very-high-performance, application-specific, real-time control systems, like automotive, HDTV image processing, and IO controller systems. The project is investigating architectures and implementations for such systems, as well as design tools to develop applications. AEDAM architectures are dedicated networks of processes. Processes can be implemented at any of the following upward compatible levels: the lowest level. Level 9, defines stateless logic. Level 1 is described by a single state vector, similar to a typical state machine. Level 2, the highest level defined yet, consists of a processor architecture with separate data and program storage. The AEDAM system allows multiple Level 2 implementations to be explored. Each of the AEDAM system components that were implemented in Smalltalk and the multiple implementations of processes which may be used in an AEDAM application are discussed. Some application areas and designs are investigated.<<ETX>>