Hans P. Tuinhout

Transistor matching in analog CMOS applications

This paper gives an overview of MOSFET mismatch effects that form a performance/yield limitation for many designs. After a general description of (mis)matching, a comparison over past and future process generations is presented. The application of the matching model in CAD and analog circuit design is discussed. Mismatch effects gain importance as critical dimensions and CMOS power supply voltages decrease.

Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors

This paper presents new insights into the mechanisms of gate depletion and boron penetration in deep submicron CMOS technologies. MOSFET matching measurements show that these effects are stochastic in nature, and are associated with the gate poly-Si grain size distribution. Moreover, this work demonstrates that these effects can strongly degrade transistor matching performance of future CMOS generations.

Effects of metal coverage on MOSFET matching

Using dedicated MOSFET matching test structures, this paper demonstrates that performance of analog as well as digital circuit blocks can degrade dramatically in multi level metal CMOS processes when transistors are covered with metal. An optimized back-end treatment improved the MOSFET matching significantly.

A comparison of extraction techniques for threshold voltage mismatch

In this paper commonly used extraction methods of MOSFET threshold voltage mismatch are compared. The V/sub T/ mismatch is extracted on the exact same device population by four independent characterization groups. Significant differences are observed, which are caused by differences in measurement setup and differences in extraction algorithm. The observed differences are analyzed. In addition merits and limitations of the various techniques are evaluated.

Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures

This paper presents a study on techniques for characterization of metal-oxide-semiconductor field-effect transistor (MOSFET) transconductance mismatch, using matched pairs with intentional 1% dimensional offsets. The relevance of this kind of work is demonstrated by the introduction of a new mismatch phenomenon that can be attributed to mechanical strain, associated with metal dummy structures that are required for backend chemical mechanical polishing (CMP) processing steps.

Test structures for investigation of metal coverage effects on MOSFET matching

An extensive set of test structures for characterization of effects of metal coverage on MOSFET matching is presented. These structures prove very useful for evaluation of MOSFET mismatch effects associated with interface states and local mechanical stress differences caused by metal lines running over matched pairs. Better understanding and control of these effects is extremely important for improving advanced mixed signal ICs in modern Multi Level Metal CMOS processes.

Accurate capacitor matching measurements using floating gate test structures

This paper discusses a new method for characterization of matching of capacitors using the so-called floating gate capacitance measurement method. The paper explains this (DC!!) measurement method and then discusses modifications that were implemented to improve the measurement accuracy and repeatability from its original thousands of ppms (0.1 to 0.3%) to values down to 50 ppm. This improved accuracy is necessary for correct characterization of capacitor matching. The method is demonstrated with results from double-polysilicon capacitor matching measurements.

The floating gate measurement technique for characterization of capacitor matching

This paper discusses a new method for characterization of matching of capacitors using the so-called floating gate capacitance measurement method. After an introduction of this measurement method, modifications are discussed that were implemented to boost the measurement accuracy and repeatability from its original thousands of ppms (0.1 to 0.3%) to values as low as 50 ppm (0.005%). Instrumental in these improvements are the introduction of a double slope measurement procedure to compensate for systematic offsets, as well as the use of repeated measurements and averaging to reduce the influence of the measurements systems noise. The improved accuracy, including statistical characterization of the measurement systems short term repeatability, are required for correct determination of capacitor matching of the extremely well-matching double-polysilicon capacitor structures that were used for this study.

A Fully Analytical MOSFET Model Parameter Extraction Approach

A direct MOSFET model parameter extraction approach is presented which IS implemented on the high volume parametric process control test system that is the standard within the PHILIPS MOS R&D environment its wel! BS in the production environrpents The major advantage of the approach is that all groups involved in the generation of circuits and drocesses, from circuit design to product engineering and from process research to production are working Vith identical MOSFET parameters. Furthermore it IS shown that the approach opens up many usehl process evaluation possibilities through wafermapping and statistical evaluation of the obtained MOSFET model parameters.

Design and characterisation of a high precision resistor ladder test structure

A new subsite stepped multiresistor test structure is introduced. This test structure is used for studying and improving small resistance mismatch patterns in resistor ladders for high-resolution analog-to-digital converter applications. By utilizing wafer prober subsite movements and contact pad cross connections in the test structures, in combination with a Kelvin measurement method and dedicated statistical data evaluation technique, this approach enables identification of very small (<0.05%) systematic resistance mismatch patterns in realistic high- precision resistor ladder implementation. The most disturbing mismatch pattern was found to be caused by mechanical stress from the resistor ladder head layout, while others are attributed to decananometer scale reticle writing artefacts.