P. Boivin

Improvement of EEPROM cell reliability by optimization of signal programming

Abstract This paper presents an optimization study of electrically erasable programmable read-only memory (EEPROM) cell programming to increase the long-term reliability of the device. Based on a charge-sheet model of the memory cell, we suggest that our result show that it is possible to decrease the electric field across the tunnel oxide of approximately 0.8 MV/cm, when using a particular programming waveform with a double rise ramp. We get the same simulated injected charge in write mode (+15 fC) and in erase mode (−12 fC) with the optimized programming signal rather than with the standard one. Threshold voltage measurements confirm the simulation results. Moreover, the endurance test shows that this new programming signal improves the endurance of the memory cell without any change in the device technology, memory cell lifetime becomes four times longer.

A new physical-based compact model of floating-gate EEPROM cells

A model for static and transient simulations of an electrically erasable programmable read-only memory (EEPROM) cell has been developed. This physical compact model is based on charge sheet approach which is able to describe the complete electrical properties of the cell. In this model the charge neutrality, including the charge trapped on the floating gate, is applied to determine the surface potential. From the surface potential, related to the terminal voltages, the drain current and the different charges present in the cell structure can be calculated. This model has been successfully implemented in common circuit simulators (Eldo and Saber) and used for the study of the write/erase operations in an EEPROM cell.

Comparison of oxide leakage currents induced by ion implantation and high field electric stress

Abstract We compare in this work the electrical properties of gate leakage currents induced through the thin SiO 2 oxide layer of metal-oxide-semiconductor structures by high-energy ion implantation (Boron B 2+ ) and high field electrical stresses where electrons are injected from the gate in the Fowler–Nordheim regime. Even if the high-frequency capacitance–voltage characteristics are very different after both treatments, comparable increases and similar shapes are found at low field in static gate current–voltage curves, typical of equivalent oxide damage. Moreover, these stress or implantation induced leakage currents are both removed in a similar way by a thermal anneal under forming gas at 430°C. We conclude that similar defects could be induced through the oxide by both processes and generate those excess currents by a defect assisted tunneling mechanism.

Conduction properties of electrically erasable read only memory tunnel oxides under dynamic stress

Abstract The write and erase programmable operations in electrically erasable read only memories (EEPROM) which are based on Fowler–Nordheim tunneling injection through a thin tunnel oxide window have been reproduced on specific large area double polycrystalline (poly) test capacitors. These structures integrate the different stacked layers (upper control gate polysilicon layer; interpoly dielectric layer; floating gate polysilicon layer; tunnel oxide; N+ substrate) of the active area of a memory cell state transistor. Stress pulses similar to those used in the programming memory cells were applied to the upper polysilicon layer. The variations of the tunnel oxide electrical conduction properties after numerous write-erase cycles were studied by measuring the current as a function of voltage characteristics of the structure. The Fowler–Nordheim constants were obtained as a function of the number of stress cycles. A model based on a simple equivalent electrical circuit was then implemented to simulate the resulting variations of the floating polysilicon gate charge and of the threshold voltage of the structure in both write and erase modes. These variations were compared to those directly measured on a memory cell. It is shown that the closure of the programmable window in memory devices can be unambiguously attributed to a decrease of the tunnel oxide conductivity.

Extraction and evolution of Fowler-Nordheim tunneling parameters of thin gate oxides under EEPROM-like dynamic degradation

Abstract A new method is presented for the extraction of the Fowler-Nordheim (FN) tunneling parameters of thin gate oxides from experimental current-voltage characteristics of Metal-Oxide-Semiconductor (MOS) capacitors. In this technique, the classical low temperature FN current model is considered but an improved numerical procedure has been implemented for the calculation of the oxide electric field — gate voltage relationship. It is shown that this iterative method leads to an excellent fit of experimental data with theoretical curves for both p-type and n-type substrates, even in the case of high doping levels. The procedure allows the determination of both FN tunneling parameters and potential barrier heights at silicon and polysilicon interfaces with a systematic estimation of the statistical fitting errors on each parameter. It is applied here to the study of the variations of the FN tunneling parameters of thin oxides submitted to EEPROM-like dynamic degradation.

Dynamic stressing of thin tunnel oxides : a way to emulate a single EEPROM cell programming function

Abstract An experimental set-up was implemented by which metal-oxide-semiconductor (MOS) capacitors are subjected to bipolar high voltage (up to 20 V) pulses similar to those used in programming electrically erasable programmable read-only memory (EEPROM) devices. Thin (9 nm) tunnel SiO2 oxides MOS capacitors were used. During stress, by means of capacitive coupling, the capacitors gate node was kept floating so its potential was equivalent to that of the isolated floating gate of a memory cell. The written and erased operations of memory cells which are based on Fowler–Nordheim (FN) tunneling injection mechanisms, were then reproduced on simple MOS capacitors. Via a high input impedance electronic circuit, the floating gate potential was monitoring. A model based on a simple equivalent electrical circuit was used to simulate the transient regime of the FN current and the resulting floating gate charge and potential during dynamic stressing. It was shown that the floating gate accumulated charge is proportional to the maximum control gate voltage but is independent of the control gate pulse rise time.

Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories

In this work, a detailed study of the physical mechanisms governing the Source Side Injection programming in ultra-scaled (down to 20nm) SiN split-gate memories is presented. Experimental measurements coupled to static and dynamic TCAD simulations are shown. In particular, we claim that adjusting the select gate voltage in moderate inversion allows for the optimization of the compromise between high electron injection and limited consumption. Then, we show that scaling the dimensions of the select gate can induce a higher consumption, while scaling the memory gate leads to lower programming energy (<;1nJ) due to higher injection efficiency, suitable for low power applications.

How to improve the silicon nanocrystal memory cell performances for low power applications

In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area coverage and SiN silicon nanocrystals capping layer are adjusted to optimize the data retention and endurance criteria. We present for the first time the endurance characteristics of a Si-nc cell up to 106 cycles with a final programming window of 4V.

Optimization of programming consumption of silicon nanocrystal memories for low power applications

In this paper we propose the optimization of the programming operation scheme of Silicon nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power applications. Using the program kinetic characteristics and a dynamic current measurement method, the programming window and the energy consumption during Channel Hot Electrons programming are deeply analyzed; evaluating ramp and box pulse with various gate and drain voltage biases. Finally the critical role of the tunnel oxide is evaluated to satisfy both retention and consumption requirements.

Extraction of band diagram parameters from Fowler–Nordheim model in silicon dioxide

Abstract In electric fields >10 7 V / cm , we have observed that the conduction current through Si( n + )/SiO 2 /poly-Si( n + ) capacitors is larger than that predicted by the classical Fowler–Nordheim law for the case of a triangular potential barrier. This phenomenon appears for both gate polarities just before electric breakdown occurs. An attempt to model this excess current by direct tunneling or by other well-known conduction mechanisms such as Schottky, Poole–Frenkel or hopping effects has been unsuccessful. We have succeeded in interpreting experimental data by considering the SiO 2 layer as a non-triangular potential barrier, which leads to a non-linear relationship between the tunneling length and the applied voltage. By using a semi-linear approach, an oxide conduction band model presenting two potential wells located at approximately from 2.5 nm to within ±0.2 nm from each oxide interface has been obtained. These two singularities may be related to the presence of a non-uniformly distributed positive charge in SiO 2 .