P. Cartujo-Cassinello

Electron transport in strained Si inversion layers grown on SiGe-on-insulator substrates

We show by simulation that electron mobility and velocity overshoot are greater when strained inversion layers are grown on SiGe-On-insulator substrates (strained Si/SiGe-OI) than when unstrained silicon-on-insulator (SOI) devices are employed. In addition, mobility in these strained inversion layers is only slightly degraded compared with strained bulk Si/SiGe inversion layers, due to the phonon scattering increase produced by greater carrier confinement. Poisson and Schroedinger equations are self-consistently solved to evaluate the carrier distribution in this structure. A Monte Carlo simulator is used to solve the Boltzmann transport equation. Electron mobility in these devices is compared to that in SOI inversion layers and in bulk Si/SiGe inversion layers. The effect of the germanium mole fraction x, the strained-silicon layer thickness, TSi, and the total width of semiconductor (Si+SiGe) slab sandwiched between the two oxide layers, Tw were carefully analyzed. We observed strong dependence of the e...

Surface roughness at the Si–SiO2 interfaces in fully depleted silicon-on-insulator inversion layers

The effect of surface roughness scattering on electron transport properties in extremely thin silicon-on-insulator inversion layers is carefully analyzed. It is shown that if the silicon layer is thin enough (thinner than 10 nm) the presence of the buried interface plays a very important role, both by modifying the surface roughness scattering rate due to the gate interface, and by itself providing a non-negligible scattering rate. The usual surface roughness scattering model in bulk silicon inversion layers is shown to overestimate the effect of the surface-roughness scattering due to the gate interface as a consequence of the minimal thickness of the silicon layer. In order to account for this effect, an improved model is provided. The proposed model allows the evaluation of the surface roughness scattering rate due to both the gate interface and the buried interface. Once the scattering rates are evaluated, electron mobility is calculated by the Monte Carlo method. The effect of the buried interface ro...

Role of surface-roughness scattering in double gate silicon-on-insulator inversion layers

The effect of surface-roughness scattering on electron transport properties in extremely thin double gate silicon-on-insulator inversion layers has been analyzed. It is shown that if the silicon layer is thin enough the presence of two Si–SiO2 interfaces plays a key role, even for a very low transverse effective field, where surface-roughness scattering is already noticeable, contrary to what happens in bulk silicon inversion layers. We have studied the electron transport properties in these devices, solving the Boltzmann transport equation by the Monte Carlo method, and analyzed the influence of the surface-roughness parameters and of the silicon layer thickness. For low transverse effective fields, μSR decreases as the silicon layer decreases. However, at higher transverse effective fields, there is a different behavior pattern of μSR with Tw since it begins to increase as Tw decreases until a maximum is reached; for lower silicon layer thicknesses, surface-roughness mobility abruptly falls. Finally we ...

Electron mobility in extremely thin single-gate silicon-on-insulator inversion layers

Inversion-layer mobility has been investigated in extremely thin silicon-on-insulator metal–oxide–semiconductor field-effect transistors with a silicon film thickness as low as 5 nm. The Poisson and Schrœdinger equations have been self-consistently solved to take into account inversion layer quantization. To evaluate the electron mobility, the Boltzmann transport equation has been solved by the Monte Carlo method, simultaneously taking into account phonon, surface-roughness, and Coulomb scattering. We show that the reduction of the silicon layer has several effects on the electron mobility: (i) a greater confinement of the electrons in the thin silicon film, which implies an increase in the phonon-scattering rate and therefore a mobility decrease; (ii) a reduction in the conduction effective mass and the intervalley-scattering rate due to the redistribution of carriers in the two subband ladders as a consequence of size quantization resulting in a mobility increase; and (iii) an increase in Coulomb scatte...

Electron mobility in double gate silicon on insulator transistors: Symmetric-gate versus asymmetric-gate configuration

We have studied electron mobility behavior in asymmetric double-gate silicon on insulator (DGSOI) inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices, where volume inversion has previously been shown to play a very important role, being responsible for the enhancement of the electron mobility. Poisson’s and Schroedinger’s equations have been self-consistently solved in these structures to study and compare the distribution of the electrons. We show that the lack of symmetry in the asymmetric DGSOI structure produces the loss of the volume inversion effect. In addition, we show that as the silicon thickness is reduced the conduction effective mass of electrons in asymmetric devices is lower than that in the symmetric case, but that the greater confinement of electrons in the former case produces a stronger increase in the phonon scattering rate, and in the surface roughness scattering rate. We have solved the Boltzmann transport equation by the Monte Carl...

Coulomb scattering model for ultrathin silicon-on-insulator inversion layers

A Coulomb scattering model for ultrathin silicon-on-insulator inversion layers has been developed. This model simultaneously takes into account (i) screening of charged centers by mobile carriers, (ii) the distribution of charged centers inside the structure, (iii) the actual electron distribution, (iv) the charged center correlation, and (v) the effect of image charges. We have used this model in a Monte Carlo simulator for single-gate silicon-on-insulator inversion layers and have calculated electron mobility curves in these devices taking into account phonon, surface roughness and Coulomb scattering for different values of the silicon slab thickness sandwiched between the two oxide layers.

Strained-Si on Si/sub 1-x/Ge/sub x/ MOSFET mobility model

A new electron mobility model for strained-Si MOSFETs has been developed. The mobility increase produced by the strain in the silicon layer is accurately studied and described by means of simple analytical expressions. This model can be easily included in conventional device and circuit simulators. The need of a surface-roughness model dependent on the germanium mole fraction is highlighted. The model fits well experimental measurements.

Deep submicrometer SOI MOSFET drain current model including series resistance, self-heating and velocity overshoot effects

We have developed a new analytical ultrashort channel SOI MOSFET for circuit simulation where the effects of series resistance, self-heating and velocity overshoot are included. We have reproduced experimental measurements validating our model. Its simplicity allowed us to study the contribution of each effect separately in an easy way.

Remote surface roughness scattering in ultrathin-oxide MOSFETs

A model to study the effect of the roughness at the poly-Si/SiO/sub 2/ interface in silicon inversion layers on the electron mobility is obtained. Screening of the resulting perturbation potential by the channel carriers is taken into account, considering Greens functions for metal-oxide-semiconductor (MOS) geometry, i.e. taking into account the finite thickness of the gate oxide. Mobility of electrons is evaluated at room temperature by the Monte Carlo method, taking into account the simultaneous contribution of phonon scattering, SiO/sub 2//Si interface roughness scattering, Coulomb scattering and remote surface roughness scattering. The contribution of excited subbands is considered. The resulting remote surface roughness scattering is shown to be strongly dependent on the oxide thickness, and degrades mobility curves at low inversion charge concentrations. The results obtained show that the effect of this scattering mechanism cannot be ignored when the oxide thickness is below 5 nm, (as in actual devices), even when (as is usual) very high doping concentrations are used.

Monte Carlo simulation of electron mobility in silicon-on-insulator structures

Abstract A Monte Carlo simulator has been used to study the electron mobility in different silicon-on-insulator structures at room and lower temperatures. Electron mobility behaviour in single-gate SOI MOSFETs is compared to that in double gate devices. The role of volume inversion is analysed. In addition, the electron mobility in strained silicon-on-SiGe-on-insulator inversion layer is also studied.