F. Jiménez-Molinos

Electron transport in strained Si inversion layers grown on SiGe-on-insulator substrates

We show by simulation that electron mobility and velocity overshoot are greater when strained inversion layers are grown on SiGe-On-insulator substrates (strained Si/SiGe-OI) than when unstrained silicon-on-insulator (SOI) devices are employed. In addition, mobility in these strained inversion layers is only slightly degraded compared with strained bulk Si/SiGe inversion layers, due to the phonon scattering increase produced by greater carrier confinement. Poisson and Schroedinger equations are self-consistently solved to evaluate the carrier distribution in this structure. A Monte Carlo simulator is used to solve the Boltzmann transport equation. Electron mobility in these devices is compared to that in SOI inversion layers and in bulk Si/SiGe inversion layers. The effect of the germanium mole fraction x, the strained-silicon layer thickness, TSi, and the total width of semiconductor (Si+SiGe) slab sandwiched between the two oxide layers, Tw were carefully analyzed. We observed strong dependence of the e...

Physical model for trap-assisted inelastic tunneling in metal-oxide- semiconductor structures

A physical model for trap-assisted inelastic tunnel current through potential barriers in semiconductor structures has been developed. The model is based on the theory of multiphonon transitions between detrapped and trapped states and the only fitting parameters are those of the traps (energy level and concentration) and the Huang–Rhys factor. Therefore, dependences of the trapping and detrapping processes on the bias, position, and temperature can be obtained with this model. The results of the model are compared with experimental data of stress induced leakage current in metal-oxide-semiconductor devices. The average energy loss has been obtained and an interpretation is given of the curves of average energy loss versus oxide voltage. This allows us to identify the entrance of the assisted tunnel current in the Fowler–Nordheim regime. In addition, the dependence of the tunnel current and average energy loss on the model parameters has been studied.

Direct and trap-assisted elastic tunneling through ultrathin gate oxides

The direct and assisted-by-trap elastic tunnel current in metal–oxide–semiconductor capacitors with ultrathin gate oxide (1.5–3.6 nm) has been studied. Bardeen’s method has been adapted to obtain the assisted tunnel current, in addition to the direct tunnel current. The dependence of the assisted current on the trap distribution in energy has also been analyzed. This allows us to obtain the trap distribution in energy from experimental current curves. Finally, we have analyzed the role of the image force, the inclusion of which can avoid a barrier height dependence on the oxide thickness.

An in-depth simulation study of thermal reset transitions in resistive switching memories

An in-depth characterization of the thermal reset transition in RRAM has been performed based on coupling self-consistent simulations to experimental results. A complete self-consistent simulator accounting for the electrical and thermal descriptions of the conductive filaments (CFs) has been developed for the numerical study of the temporal evolution of the reset transition in RRAM. The CFs series resistance, including the contributions of the setup and Maxwell components, has been included in the calculations. Using this simulation tool, we have been able to reproduce many experimental details of the experimental reset data obtained in Cu/HfO2/Pt devices. In doing so, we explained the current steps observed in some reset cycles by considering CFs with several coupled branches that break down at different times. The reset voltage dependence on the initial resistance of the CF has been analyzed and the relevant role played by the CF shape has also been demonstrated. In this respect, devices with a same in...

Simulation of thermal reset transitions in resistive switching memories including quantum effects

An in-depth study of reset processes in RRAMs (Resistive Random Access Memories) based on Ni/HfO2/Si-n+ structures has been performed. To do so, we have developed a physically based simulator where both ohmic and tunneling based conduction regimes are considered along with the thermal description of the devices. The devices under study have been successfully fabricated and measured. The experimental data are correctly reproduced with the simulator for devices with a single conductive filament as well as for devices including several conductive filaments. The contribution of each conduction regime has been explained as well as the operation regimes where these ohmic and tunneling conduction processes dominate.

Coulomb scattering model for ultrathin silicon-on-insulator inversion layers

A Coulomb scattering model for ultrathin silicon-on-insulator inversion layers has been developed. This model simultaneously takes into account (i) screening of charged centers by mobile carriers, (ii) the distribution of charged centers inside the structure, (iii) the actual electron distribution, (iv) the charged center correlation, and (v) the effect of image charges. We have used this model in a Monte Carlo simulator for single-gate silicon-on-insulator inversion layers and have calculated electron mobility curves in these devices taking into account phonon, surface roughness and Coulomb scattering for different values of the silicon slab thickness sandwiched between the two oxide layers.

A comprehensive analysis on progressive reset transitions in RRAMs

Reset processes in resistive random-access memory devices have been studied in depth. In particular, progressive transitions, where no clear current reduction steps are seen, are analysed by using a previously developed simulator and by comparing with experimental data of devices based on HfO2 oxides. It has been reported that the characterization of progressive reset processes can be performed by separately considering devices with a single conductive filament or devices with more than one conductive filament. In addition, making use of the experimental measurements shown, different numerical methods are proposed to extract the reset voltage. These methods are applied to different I–V reset curves and discussed.

A SPICE Compact Model for Unipolar RRAM Reset Process Analysis

A physically based circuit model is proposed for SPICE simulation of thermally assisted reset transitions in resistive switching devices. The model allows the simulation of conductive filaments with complex structures, such as a main filament with several subfilaments attached forming a tree structure, or several filaments interlaced between them. The model has been validated by comparing with experimental data and the simulations obtained with a previously published simulation tool. A study of the influence of different subfilaments configurations on the variability of resistive random access memory I-V reset curves is also presented.

An Analytical

A new analytical model is presented for the inversion charge of surrounding-gate transistors (SGTs). Quantum effects are taken into account by means of a modified capacitance model that includes the inversion charge centroid and a correction to the threshold voltage. A drain current model for the SGT that includes velocity saturation, short channel, and velocity overshoot effects is also developed. The model accurately reproduces both simulated and experimental results for different silicon core radii and gate voltages.

I

A new model for calculating Coulomb perturbation potentials in bidimensional semiconductor structures is proposed. The main advantage of this model is that it can be applied for an arbitrary number of layers with different permittivities. As an example of how it could be used, we studied the influence on Coulomb scattering of high-κ materials used as gate insulators in silicon-on-insulator structures. This study was carried out with insulators of different physical and effective oxide thicknesses. The results show that when a silicon dioxide is replaced by a high-κ dielectric with the same thickness, Coulomb scattering is reduced. However, the strength of this beneficial effect might be diminished in actual devices for two reasons. The first is that an interfacial layer of silicon dioxide is usually placed between the silicon slab and the high-κ dielectric, lessening its influence. Second, a gate high-κ dielectric is normally wider than its silicon dioxide counterpart. As a consequence, the metal or polys...