P. Chiquet

Robustness of the floating-gate technique in a very low-noise environment

In this paper we present the development of a cheap test bench to make the acquisition of very low leakage currents in Non-volatile memories. This test bench is embedded in a very particular low-noise environment to reduce ambient vibrations and electromagnetic perturbations. We will principally discuss the robustness of the full experiment concerning the acquisition conditions (integration time and number of measurements, choice of applied biases). Finally we will present the extraction steps and the resulting leakage current, below every direct measurement.

Charge loss activation during non-volatiles memory data retention

In this paper we develop a method to study and to activate charge loss in a Non-volatile Memories array. We first detail an original date retention test under gate stress on a simple and statistical tool. Then we present the experimental results we obtained after more than 700h at 85°C and 150°C, for six different gate stress conditions. Finally, we extract the activation energy for the observed charge losses, using to different approaches, leading to a discussion on the extracted values and to perspectives for this work.

Simulation of the programming efficiency and the energy consumption of Flash memories during endurance degradation

In this paper the impact of the endurance degradation on the programming window and the energy consumption of Flash floating gate memories is investigated. We use TCAD simulations to confirm, predict and explain the behavior we have observed in previous experimental studies. These simulations have been developed for 90nm technology node Flash floating gate memories, but they are fully compatible with highly scaled devices. The use of interface traps in the simulation enables to reproduce the increase in the drain current consumption and the decrease in the programming efficiency after endurance degradation. Moreover, we highlight the fact that after degradation the hot electrons energy and velocity are lower, decreasing the electrons injection in the floating gate.

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction

Abstract Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40 nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both drain and bulk currents are measured and monitored throughout the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with an equivalent transistor. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field o...

NVM cell degradation induced by femtosecond laser backside irradiation for reliability tests

In this paper we present the behavior of a single nonvolatile Flash floating gate memory cell when it is irradiated, from the backside, by femtosecond laser pulses. For the first time we show that the memory cell state can change using this type of stimulation. The measurements were carried out with an experimental setup with an ad hoc probe station built around the optical bench. We present the experimental results using different memory bias conditions to highlight the charge injection in the floating gate. Then, we study the cell degradation to check the state of the tunnel oxide and the drain-bulk junction. The aim is to understand the failure mechanisms and use this technique for accelerated reliability tests. Finally we report the experimental results achieved for different laser energies.

Indirect measurement of low tunneling currents through dielectrics using Floating Gate structures

In this paper we propose and develop a complete solution to measure very low tunneling currents in Non-Volatile Memories, based on the Floating-Gate technique. We aim at using very basic tools (power supply, multimeter...) but still having a very good current resolution. The key node of our solution is that the experiment is led in a very particular low-noise environment (underground laboratory) allowing to keep the electrical contacts on the device under test as long as possible. The aim of this work is to show both the feasibility of such measurements and the ability to reach current levels lower than the ones obtained by any direct measurement, even from high-performance devices such as HP4156 or Keysight B1500 with atto-sense and switch unit (ASU). We have obtained the complete I-V characteristics of tunnel oxide with a very promising 10-17A current level, two decades lower than any direct measurement.

Improving Flash memory endurance and consumption with ultra-short channel-hot-electron programming pulses

In this paper we propose to modify the pulses classically used during the channel-hot-electron programming phase of a Flash memory and to replace it by a sequence of ultra-short pulses in order to decrease the programming window closure observed during the endurance test. We start this work presenting the other solutions published in literature. Then, we describe our advanced measurement setup and finally we show our experimental results. Furthermore we evaluate the impact of these ultra-short pulses on the current consumption during the programming phase.

Determination of physical properties of semiconductor-oxide-semiconductor structures using a new fast gate current measurement protocol

A new experimental protocol involving fast tunneling current measurements has been set up to highlight various physical properties of the floating gate / tunnel oxide / drain capacitor of Non-Volatile Memory (NVM) devices. Transient gate currents obtained on n++/siO2/n+ MOS capacitors representative of the real device for negative gate signals are interpreted and successfully modeled.