F. Lalande

Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories

In this paper we propose to study different ways to extract the values of parasitic capacitances in 90 nm and 22 nm NAND Flash memories. Indeed, these parasitic capacitances between cells in the array can modify applied polarizations and can disturb the functioning of the whole array. Their impact increases when the cell size is reduced, especially as the ultimate size of the 22 nm node is reached. We develop 3D TCAD simulations to extract parasitic capacitances as well as measurements on specific test structures or geometrical calculations, showing their increasing importance in the future technologies, especially for 22 nm node.

A Modelisation of the temperature dependence of the Fowler–Nordheim current in EEPROM memories

Abstract In this paper, we suggest a new computation method to simulate the temperature behavior of Fowler–Nordheim tunneling current through the oxide of an EEPROM cell based on surface potential evaluation with temperature dependence. The main idea of this paper is to simulate the tunneling current temperature dependence with only Si–SiO 2 barrier height and surface potential dependences with temperature. Parameters are experimentally extracted from large SOS capacitor measurements. So, final results of the programming window have shown comparing to simulations and measurements.

Energy consumption optimization in nonvolatile silicon nanocrystal memories

In this paper we investigate the energy consumption of Discrete-Trap Silicon Nanocrystal (Si-nc) Nonvolatile Memory Cell during Channel Hot Electron programming operation. We compare this cell with a Floating Gate Flash in order to evaluate the current absorption and the energy consumption under different conditions. Using a commercial TCAD simulator, a good agreement between data and simulations is obtained and the involved mechanisms are analysed. Then we propose a solution to optimize the programming window and energy consumption trade-off for Si-nc Flash Cells.

Modeling charge variation during data retention of MLC Flash memories

Abstract In this paper, we propose to model charge variation in Multi-Level Cells in NOR Flash memories. We first define a sensitivity-to-temperature factor to determine the number of involved mechanisms. Then, according to previous studies, we can use the Poole–Frenkel (PF) and/or the Fowler–Nordheim (FN) equations to model every charge loss, which we apply to our cells. We succeed in modeling our data retention measurements by superimposing these two phenomena, being, respectively preponderant at the beginning and at the end of the data retention measurements, as shown by the factor of sensitivity-to-temperature. We have then found a relationship between temperatures to evaluate our cells lifetime. We validate that the classical 1/T Arrhenius law is not the most appropriate and that a T model can be better. We also model a fictive charge gain by using a negative charge front displacement in the tunnel oxide. This study can easily be extended to any floating gate non-volatile memory.

A Full TCAD simulation and 3D parasitic capacitances extraction in 90nm NAND flash memories

In this paper we propose a way to study the degradation mechanism of ¿inhibited¿ cells during the cycling of ¿selected¿ cells in 90 nm NAND Flash memories. This degradation is a main issue in NAND Flash memories reliability. To explain this degradation, we first develop a 2D TCAD cell simulation to watch attentively what happens in the channel where measurements are impossible. Some phenomena are shown here which could begin to explain what occurs. Because of continual shrinking, coupling capacitances between cells in the array have a significant impact on the cell behaviour. The previous simulation can be completed by taking into account these 3D parasitic capacitances which have been extracted in a second time.

Leakage paths identification in NVM using biased data retention

Abstract In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.

How to improve the silicon nanocrystal memory cell performances for low power applications

In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area coverage and SiN silicon nanocrystals capping layer are adjusted to optimize the data retention and endurance criteria. We present for the first time the endurance characteristics of a Si-nc cell up to 106 cycles with a final programming window of 4V.

Optimization of programming consumption of silicon nanocrystal memories for low power applications

In this paper we propose the optimization of the programming operation scheme of Silicon nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power applications. Using the program kinetic characteristics and a dynamic current measurement method, the programming window and the energy consumption during Channel Hot Electrons programming are deeply analyzed; evaluating ramp and box pulse with various gate and drain voltage biases. Finally the critical role of the tunnel oxide is evaluated to satisfy both retention and consumption requirements.

Charge loss activation during non-volatiles memory data retention

In this paper we develop a method to study and to activate charge loss in a Non-volatile Memories array. We first detail an original date retention test under gate stress on a simple and statistical tool. Then we present the experimental results we obtained after more than 700h at 85°C and 150°C, for six different gate stress conditions. Finally, we extract the activation energy for the observed charge losses, using to different approaches, leading to a discussion on the extracted values and to perspectives for this work.

Experimental study to push the Flash floating gate memories toward low energy applications

The problem of energy saving has today a relevant importance, concerning in particular all the portable devices as smart phone, tablet PC, smart card and so on [1]. In order to improve the features of these products, particular attention is paid to energy consumption of Flash cells in memory arrays. In this work we investigated the Flash floating gate (FG) dynamic behavior during the channel hot electron (CHE) programming operation. After this, we propose a solution to optimize the energy consumption. The samples studied in this experimental work are Flash floating gate memory cells (embedded NOR flash process). The ONO inter-poly dielectric stack has an equivalent thickness of 14nm, while the tunnel oxide of 9.5nm is grown on a p-type silicon substrate. We evaluated the variation effect of two important technological parameters: channel doping dose (CDD) and lightly doped drain (LDD) energy implantation.