G. Micolau

A Modelisation of the temperature dependence of the Fowler–Nordheim current in EEPROM memories

Abstract In this paper, we suggest a new computation method to simulate the temperature behavior of Fowler–Nordheim tunneling current through the oxide of an EEPROM cell based on surface potential evaluation with temperature dependence. The main idea of this paper is to simulate the tunneling current temperature dependence with only Si–SiO 2 barrier height and surface potential dependences with temperature. Parameters are experimentally extracted from large SOS capacitor measurements. So, final results of the programming window have shown comparing to simulations and measurements.

Analysis of SEU parameters for the study of SRAM cells reliability under radiation

A simplified RC circuit is used to simulate the effects of ionizing particles in a 90nm SRAM. The main characteristic of the memory cell bit flip are discussed and compared for characteristic parameters. The effect of the surrounded circuit on the impacted transistor is discussed in order to extract parameters characteristic of the SEU occurrence.

Investigation of a CMOS oscillator concept for particle detection and diagnosis

An oscillator concept used for particle detection and diagnosis is presented. The methodology used to characterize the currents generated by particles is detailed and the results extracted from a DOE analysis are presented.

Leakage paths identification in NVM using biased data retention

Abstract In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.

SITARe: A simulation tool for analysis and diagnosis of radiation effects

This work provides reliability criteria to detect and diagnose multi-events upset by the use of a SER tool. The study is based on a charge generation model used to simulate the impact of an ionizing particle striking the sensitive nodes of a SRAM cell. The currents, collected at the sensitive nodes are generated by the physical model and injected at circuit level. Thus, a correlation between the circuit electrical behavior and injected currents is established to provide a reliability criterion.

Impact of SEU configurations on a SRAM cell response at circuit level

This work focuses on the SEU simulation in a 90nm SRAM cell, in order to provide basic metrics for reliability studies. To do that, a charge generation model is used to simulate the impact of an ionizing particle striking a sensitive node. The current collected at this particular node is extracted and injected at a circuit level. Thus, a correlation between the circuit electrical behavior and the critical charge is presented.

Robustness of the floating-gate technique in a very low-noise environment

In this paper we present the development of a cheap test bench to make the acquisition of very low leakage currents in Non-volatile memories. This test bench is embedded in a very particular low-noise environment to reduce ambient vibrations and electromagnetic perturbations. We will principally discuss the robustness of the full experiment concerning the acquisition conditions (integration time and number of measurements, choice of applied biases). Finally we will present the extraction steps and the resulting leakage current, below every direct measurement.

Charge loss activation during non-volatiles memory data retention

In this paper we develop a method to study and to activate charge loss in a Non-volatile Memories array. We first detail an original date retention test under gate stress on a simple and statistical tool. Then we present the experimental results we obtained after more than 700h at 85°C and 150°C, for six different gate stress conditions. Finally, we extract the activation energy for the observed charge losses, using to different approaches, leading to a discussion on the extracted values and to perspectives for this work.

Fast extraction of extrinsic cells in a NVM array after retention under gate stress

As NVM technology gains maturity, new application fields emerge, often implying new product requirements, especially at high temperature. The data retention is a key criterion for good reliability cells. Many previous studies have already dealt with the charge leakage but some of them seem to show a leakage through SiO2 tunnel oxide [1] while others seem to show a leakage through ONO [2]. We have already proposed an experimental way to identify the involved paths by biasing the cell during data retention [3]. The applied bias is used to cancel either the electric field across tunnel oxide or across ONO, depending on the sign of this bias.

Contribution to SER prediction: A new metric based on RC transient simulations

This work focuses on speeding up simulation time of SEU systematic detection in a 90 nm SRAM cell. Simulations were run in order to validate a simplified approach based on the injection of a noise source current at the sensitive node of an analytical RC circuit. Moreover, a new SEU reliability metric, mandatory for reliability studies, is introduced. It is based on based on transient I–V simulations.