P. David Fisher

The token-skipping channel access scheme for bus networks

Abstract A major disadvantage of the standard token-bus network architecture is the delay involved in passing the token through idle stations. A modified token-passing scheme is described that minimizes this overhead by bypassing idle stations. This scheme requires very little additional hardware over the proposed IEEE 802.4 channel-access protocol and has this proposed standard protocol as one of its limiting cases. Simulation studies of this scheme show significant improvement of delay-throughput characteristics for practical load ranges. For example, for throughputs up to about 65%, a network with 100 nodes with Poisson arrivals and symmetric load distribution among nodes has a mean delay of less than half that of a similar network using the conventional token-passing scheme. Under asymmetric load distribution among nodes, even higher speedup factors can be achieved.

Law enforcement: Shortcomings of radar speed measurement: It's based on sound principles, but present systems have practical limitations and may be misused

Well-publicized court rulings have found radar speed readings inadmissible as legal evidence, because the radars were operated in such a way as to cast doubt on the accuracy of the readings. Existing devices are, in fact, quite accurate if used within their limitations by trained operators. The problems can be overcome through better training and tighter equipment standards, while some relatively simple technical improvements in the radars can reduce present limitations significantly.

The modified CORDIC algorithm

A Modified CORDIC Algorithm (MCA) has been developed for the evaluation of elementary arithmetic functions. MCA incorporates increased parallelism over the original CORDIC algorithm, thus, resulting in an enhanced speed of computation. This has been accomplished by decoupling the CORDIC interation equations and transforming the sequential nature of these equations, n-bit fixed point data operands are assumed and the parameter k relates to the level of parallelism in the algorithm. The modified algorithm employs a [k+1]n2 n-bit ROM for lookup tables that enable elementary arithmetic functions to be evluated in no more than [3n+2] and no less than 2 time steps. The two bounds correspond to a pipelined and a parallel implementation, respectively. The formulation of the MCA can be manipulated to obtain implementations with various speed/cost characteristics. This compares to n(3n+1)/2 time steps for the original CORDIC algorithm. For example, 32-bit ALU has k=12 and n=32; so, a 13,312-bit ROM is required to store the lookup tables, and the computation requires 98 time steps for a pipelined implementation.

Computational design alternatives with microprocessor-based systems

This paper examines and characterizes four elemental hardware computational design alternatives (CDAs) and presents a structured approach to computational section design which incorporates a rigorous, theoretic foundation. The DIRECT CDA incorporates a single microprocessor (μP) and memory. The AU CDA contains a μP, memory, and arithmetic unit. A μP, memory, and calculator chip comprise the CALC CDA. Finally, several μPs and memories in a Master/Slave arrangement implement the multiple-μP mμP CDA. A common set of attributes — precision, speed and cost — facilitates comparison. Using these attributes, Multiattribute Utility Theory assesses a numeric quantity, the utility, to represent each CDAs relative usefulness. Thus, design involves selecting the CDA with the greatest utility.