P. De Remigis

Fast bipolar front-end for binary readout of silicon strip detectors

A very fast low-noise low-power 64-channel front-end chip for binary readout of silicon microstrip detectors (FABRIC) has been designed and manufactured using the full-custom bipolar process SHPi by Tektronix. The circuit consists of a preamplifier, a shaper and a discriminator. A noise level of 476 e− + 63 e−/pF has been obtained for the amplifier peaking time of 15 ns. The walk time of the discriminator is less than 5 ns for input signals ranging from 2 fC to 8 fC at a discriminator threshold of 1 fC. The dead time for two minimum ionizing particle signals is 40 ns. The above parameters have been obtained with a low power consumption of 1.3 mW per channel.

The first level trigger of the OBELIX spectrometer

Abstract The first level trigger of the OBELIX (PS 201) experiment is described. Based on the time of flight system (TOF) of the detector and including modules designed for the purpose, we have built and operated a system capable of selecting simple prespecified hit patterns within 200 ns.

A fast, high-granularity silicon multiplicity detector for the NA50 experiment at CERN

Abstract We have designed a silicon detector to measure the angular distribution and the multiplicity of charged secondaries produced in high-energy PbPb interactions. It will be used to characterize the events in the NA50 experiment. The experiment will have to function at very high rate, and the silicon detectors will have to operate in the high-radiation area close to the target. Therefore, the detector will have to be very fast (dead time below 50 ns), radiation resistant (up to the Mrad level as dose and up to more than 1013 particles/cm2 as non-ionizing damage) and of high granularity. The conditions on noise, speed and radiation hardness are comparable to the ones foreseen at the future Large Hadron Collider at CERN. We present here the detector design, discuss some of the solutions which have been investigated and report first results on the components of the system which have been designed and produced up to now.

A silicon pixel readout ASIC in CMOS 0.13 μm for the PANDA microvertex detector

The requirements for the PANDA Micro Vertex Detector in terms of track density and absence of a trigger signal lead to the need of a custom solution for the electronic readout of the silicon pixel detectors. A reduced scale prototype with two 128 cells and two 32 cells columns has been designed in a CMOS 0.13 μm technology and successfully tested. The ASIC measures the 2-D position, the hit arrival time and the charge released via a Time over Threshold technique.

Image Compression for the Silicon Drift Detectors in the ALICE Experiment

Abstract We describe an algorithm for the zero suppression and data compression for the Silicon Drift Detectors (SDD) in the ALICE experiment. The algorithm operates on 10-bit linear data streams from the SDDs by applying a 10 bit to 8-bit non-linear compression followed by a data reduction based on a two-threshold discrimination and a two-dimensional analysis along both the drift time and the anodes. The proposed scheme allows for a better understanding of the neighborhoods of the SDD signal clusters, thus improving their reconstructability, and also provides a statistical monitoring of the background characteristics for each SDD anode. The entire algorithm is purely combinatorial and thus can be executed in pipeline, without additional clock cycles, during the SDD readout. The hardware coding together with the methods for the expansion to the original 10-bit values in the offline analysis and for the background monitoring are presented.

A CMOS 0.13μm Silicon Pixel Detector Readout ASIC for the PANDA experiment

The ToPiX ASIC is a custom development for the hybrid pixel sensors of the PANDA experiment Micro Vertex Detector. The ASIC will provide both the time and amplitude informations (via the Time over Threshold technique) of the incoming particle. ToPiX will consist of a matrix of 116 × 110 cells with a pixel size of 100 × 100 μm2, the column readout logic and two 311 Mbit/s serializers. A reduced scale prototype in CMOS 0.13 μm has been designed and tested. The prototype includes eight columns with the full cell analogue and digital circuitry and the end of column readout.

Operation and calibration of the Silicon Drift Detectors of the ALICE experiment during the 2008 cosmic ray data taking period

The calibration and performance of the Silicon Drift Detector of the ALICE experiment during the 2008 cosmic ray run will be presented. In particular the procedures to monitor the running parameters (baselines, noise, drift speed) are detailed. Other relevant parameters (SOP delay, time-zero, charge calibration) were also determined.

Charge collection in the Silicon Drift Detectors of the ALICE experiment

A detailed study of charge collection efficiency has been performed on the Silicon Drift Detectors (SDD) of the ALICE experiment. Three different methods to study the collected charge as a function of the drift time have been implemented. The first approach consists in measuring the charge at different injection distances moving an infrared laser by means of micrometric step motors. The second method is based on the measurement of the charge injected by the laser at fixed drift distance and varying the drift field, thus changing the drift time. In the last method, the measurement of the charge deposited by atmospheric muons is used to study the charge collection efficiency as a function of the drift time. The three methods gave consistent results and indicated that no charge loss during the drift is observed for the sensor types used in 99% of the SDD modules mounted on the ALICE Inner Tracking System. The atmospheric muons have also been used to test the effect of the zero-suppression applied to reduce the data size by erasing the counts in cells not passing the thresholds for noise removal. As expected, the zero suppression introduces a dependence of the reconstructed charge as a function of drift time because it cuts the signal in the tails of the electron clouds enlarged by diffusion effects. These measurements allowed also to validate the correction for this effect extracted from detailed Monte Carlo simulations of the detector response and applied in the offline data reconstruction.

The ToPiX v4 prototype for the triggerless readout of the PANDA silicon pixel detector

ToPiX v4 is the prototype for the readout of the silicon pixel sensors for the Micro Vertex Detector of the PANDA experiment. ToPiX provides position, time and energy measurement of the incoming particles and is designed for the triggerless environment foreseen in PANDA. The prototype includes 640 pixels with a size of 100 × 100 μm2, a 160 MHz time stamp distribution circuit to measure both particle arrival time and released energy (via ToT technique) and the full control logic. The ASIC is designed in a 0.13 μm CMOS technology with SEU protection techniques for the digital parts.

Single-event upset tests on the readout electronics for the pixel detectors of the PANDA experiment

The Silicon Pixel Detector (SPD) of the future PANDA experiment is the closest one to the interaction point and therefore the sensor and its electronics are the most exposed to radiation. The Total Ionizing Dose (TID) issue has been addressed by the use of a deep-submicron technology (CMOS 0.13 μm) for the readout ASICs. While this technology is very effective in reducing radiation induced oxide damage, it is also more sensitive to Single Event Upset (SEU) effects due to their extremely reduced dimensions. This problem has to be addressed at the circuit level and generally leads to an area penalty. Several techniques have been proposed in literature with different trade-off between level of protection and cell size. A subset of these techniques has been implemented in the PANDA SPD ToPiX readout ASIC prototypes, ranging from DICE cells to triple redundancy. Two prototypes have been tested with different ion beams at the INFN-LNL facility in order to measure the SEU cross section. Comparative results of the SEU test will be shown, together with an analysis of the SEU tolerance of the various protection schemes and future plans for the SEU protection strategy which will be implemented in the next ToPiX prototype.