Thanushan Kugathasan

A silicon pixel readout ASIC in CMOS 0.13 μm for the PANDA microvertex detector

The requirements for the PANDA Micro Vertex Detector in terms of track density and absence of a trigger signal lead to the need of a custom solution for the electronic readout of the silicon pixel detectors. A reduced scale prototype with two 128 cells and two 32 cells columns has been designed in a CMOS 0.13 μm technology and successfully tested. The ASIC measures the 2-D position, the hit arrival time and the charge released via a Time over Threshold technique.

A CMOS 0.13μm Silicon Pixel Detector Readout ASIC for the PANDA experiment

The ToPiX ASIC is a custom development for the hybrid pixel sensors of the PANDA experiment Micro Vertex Detector. The ASIC will provide both the time and amplitude informations (via the Time over Threshold technique) of the incoming particle. ToPiX will consist of a matrix of 116 × 110 cells with a pixel size of 100 × 100 μm2, the column readout logic and two 311 Mbit/s serializers. A reduced scale prototype in CMOS 0.13 μm has been designed and tested. The prototype includes eight columns with the full cell analogue and digital circuitry and the end of column readout.

Monolithic pixel development in 180 nm CMOS for the outer pixel layers in the ATLAS experiment

The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

A 15μW 12-bit dynamic range charge measuring front-end in 0.13μm CMOS

A 100μm × 100μm readout cell with a power consumption of 15μW and optimized for 12 bits dynamic range is presented. This circuit has been developed to readout the hybrid pixel sensors for the Micro-Vertex Detector (MVD) of the PANDA experiment at GSI. The readout architecture is based on the Time-over-Threshold technique which allows to achieve low-power charge measurement with a high dynamic range. The front-end has been designed to handle input charges up to 100f C. The analog building blocks are described in detail, focusing the attention on the main design challenges: the dynamic range limitation, the implementation of a compact filter for the leakage compensation, and the management of the mismatch effects. A first prototype has been designed and produced in a CMOS 0.13μm technology and the test results are discussed. Given the very low-power consumption and the small size of the readout cell it is interesting to employ it as a compact digitizer for other applications. Preliminary studies have been done to extend this concept to the readout of double sided strip sensors of the PANDA MVD.

Electrical and functional characterisation with single chips and module prototypes of the 1.2 Gb/s serial data link of the monolithic active pixel sensor for the upgrade of the ALICE Inner Tracking System

The upgrade of the ALICE Inner Tracking System uses a newly developed monolithic active pixel sensor (ALPIDE) which will populate seven tracking layers surrounding the interaction point. Chips communicate with the readout electronics using a 1.2 Gb/s data link and a 40 Mb/s bidirectional control link. Event data are transmitted to the readout electronics over microstrips on a Flexible Printed Circuit and a 6 m long twinaxial cable. This paper outlines the characterisation effort for assessing the Data Transmission Unit performance of single sensors and prototypes of the detector modules. It describes the different prototypes used, the test system and procedures, and results of laboratory and irradiation tests.

LAPA, a 5 Gb/s modular pseudo-LVDS driver in 180 nm CMOS with capacitively coupled pre-emphasis

A pseudo-LVDS driver has been designed in a 180 nm technology for operation up to 5 Gb/s. It contains parallel main driver units based on an H-bridge circuit steering a current on an external load. The number of active units is adjustable, to reduce switching capacitance and static current, and hence power consumption, if a smaller current swing can be tolerated. Pre-emphasis is applied with a capacitively coupled charge-injection circuit. In the nominal condition with a steering current of 4 mA over a 100

arXiv : Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

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Triggerless readout architecture for the silicon pixel detector of the PANDA experiment

termination resistor, it consumes 30 mW from a 1.8 V supply.

Hybrid pixel detector with epitaxial sensors and readout in 130 nm CMOS technology for PANDA

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

The silicon pixel system for the Micro Vertex Detector of the PANDA experiment

The readout architecture for the silicon pixel detector of the PANDA MVD (Micro Vertex Detector) is presented. The pixel detector has to provide timing, position and energy information on a event-driven base, since no trigger signal is foreseen. The readout system is based on a custom ASIC, named ToPiX, directly connected to the GBT (GigaBit Transceiver) optical transceiver. A reduced size prototype with most of the main functionalities has been designed and tested. The ASIC has been bonded to a sensor based on the epitaxial technology and tested on a beam test. TID (Total Ionizing Dose) tests on the ToPiX prototype have been performed.