P. J. Chen

Low voltage stress-induced-leakage-current in ultrathin gate oxides

Stress-induced-leakage-current (SILC) is an important concern in ultrathin gate oxides because it may impose constraints on dielectric thickness scaling. We show that for oxides less than /spl sim/3.5 nm thick, interfacial traps generated from direct tunneling stress result in a sense voltage dependent SILC mechanism that can dominate the gate leakage current at low operating voltages.

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs

HfO/sub 2/ nMOSFETs and pMOSFETs were fabricated using scaled chemical oxides as a starting interface, together with sputtered (PVD) TiN gate electrodes. Aggressively scaled stacks of 8.2 /spl Aring/ EOT on nMOS and 7.5 /spl Aring/ EOT on pMOS were achieved with leakage current of <5 A/cm/sup 2/ at V/sub FB/ +1 volts. Low fixed charge density in the HfO/sub 2/ layer was observed from VFB extraction, using high frequency-CV measurements, when considering a TiN workfunction of 4.78 eV. Conventional C-V hysteresis and transient V/sub T/ instability measurements on sub 1 nm TiN/HfO/sub 2/ devices indicated reduced instability as a result of EOT scaling. The electron mobility is degraded with EOT scaling whereas hole mobility remains constant down to an EOT of 8 /spl Aring/.

ELECTRICAL AND PHYSICAL CHARACTERIZATION OF DEUTERIUM SINTER ON SUBMICRON DEVICES

The impact of a deuterium (D2) sinter under two different annealing conditions, 450 °C/60 min and 450 °C/90 min, was studied and compared to the traditional forming gas (FG) sinter. Channel hot carrier (CHC) measurements indicated that while the D2 sinter for 60 min improves the lifetime of the devices by 10× over the FG sinter, an additional increase in the D2 anneal time actually has a negative impact on lifetime. DC current–voltage measurements also showed that samples sintered in D2 ambient for 60 min were the least prone to degradation under stress. Gated diode results showed no appreciable amount of difference in the initial interface state density among the different samples. Secondary ion mass spectroscopy indicated that neither poly nor salicide appears to be a complete barrier to D2 diffusion.

Examination of deuterium transport through device structures

We use secondary ion mass spectrometry to characterize the hydrogen/deuterium distribution and concentration on 0.18 μm “metal” oxide silicon test structures subjected to deuterium anneals. We examine the temperature dependence and the influence of doping on the transport of deuterium to the gate oxide interfaces resulting in interface passivation. We find that undoped polycrystalline silicon appears to be an efficient barrier for deuterium transport at typical postmetallization sintering temperatures.

Deuterium transport through device structures

We use secondary ion mass spectrometry to characterize the hydrogen/deuterium distribution and concentration on complimentary “metal” oxide silicon (CMOS) test structures subjected to molecular deuterium (D2) anneals. We examine the temperature dependence and the influence of doping on the transport of deuterium to the gate oxide interfaces resulting in interface passivation. We find that undoped polycrystalline silicon appears to be an efficient barrier for deuterium transport at typical postmetallization sintering temperatures. We also examine the permeability of device structures that include dielectric encapsulation layers after typical postmetal sintering conditions employed in a conventional CMOS process flow. It is found that typical low temperature deposited oxide dielectrics are quite permeable by molecular deuterium at typical sintering temperatures (435 °C). In contrast, chemical vapor deposited silicon nitride dielectrics appear to form a complete barrier to deuterium diffusion (even for layers as thin as 300 A). We also find that nitrides which receive a high thermal budget exposure, such as the source/drain anneal, appears to regain permeability to deuterium diffusion/transport.We use secondary ion mass spectrometry to characterize the hydrogen/deuterium distribution and concentration on complimentary “metal” oxide silicon (CMOS) test structures subjected to molecular deuterium (D2) anneals. We examine the temperature dependence and the influence of doping on the transport of deuterium to the gate oxide interfaces resulting in interface passivation. We find that undoped polycrystalline silicon appears to be an efficient barrier for deuterium transport at typical postmetallization sintering temperatures. We also examine the permeability of device structures that include dielectric encapsulation layers after typical postmetal sintering conditions employed in a conventional CMOS process flow. It is found that typical low temperature deposited oxide dielectrics are quite permeable by molecular deuterium at typical sintering temperatures (435 °C). In contrast, chemical vapor deposited silicon nitride dielectrics appear to form a complete barrier to deuterium diffusion (even for layer...

Valence-band electron-tunneling measurement of the gate work function: Application to the high-κ/polycrystalline-silicon interface

A technique is demonstrated to measure the band alignment between the silicon substrate and the gate electrode using the valence-band electron tunneling (VBET). When an n-channel metal-oxide-semiconductor field-effect transistor is biased in inversion the valence-band electron from the Si substrate can tunnel into the gate [A. Shanware, J. Shiely, H. Massoud, E. Vogel, K. Henson, A. Srivastava, C. Osburn, J. Hauser, and J. Wortman, Tech. Dig.-Int. Electron Devices Meet.1999, 815], depending on the overlapping of the density of states in the Si valence band and the gate. This technique is suitable to measure the band alignment between the silicon substrate and the gate electrode with any given gate dielectric, provided that both the gate and substrate leakages are dominated by direct tunneling. This technique has been applied to study the SiO2/polycrystalline-silicon (poly-Si) interface behavior in the presence of submonolayer traces of HfO2. The general applicability of VBET to arbitrary gate stacks is fi...

Thermal stability and scalability of Zr-aluminate-based high-k gate stacks

It is demonstrated that a narrow composition range exists in the ZrAl/sub x/O/sub y/ mixed oxide system between 25 and 50 mol% Al/sub 2/O/sub 3/, where the crystallization temperature exceeds 950/spl deg/C and at the same time the k-values remain larger than 12. In this composition range, enhanced thermal stability for better integration of the ZrAl/sub x/O/sub y/ gate dielectric in a conventional poly-Si device process is observed. It is also shown that thin interfacial oxides strongly enhance the electrical stability while allowing for thickness scaling down to /spl sim/1 nm, providing gate leakage current reductions of two to three orders of magnitude.

Adsorption of perfluorinated n‐alkanoic acids on native aluminum oxide surfaces

We have examined the reaction of solution and vacuum vapor deposited long chain perfluorinated n‐alkanoic acids CF3(CF2)nCOOH (n=8–16) with the native aluminum‐oxide surface using x‐ray photoelectron spectroscopy and infrared reflection absorption spectroscopy. Adsorption from solution results in slightly higher acid surface coverage than that achieved from vacuum deposition. We also find that adsorption of acids from either deposition method results in a canted, monodentate configuration. Thermal degradation is observed from the elevated temperatures employed in the vacuum deposition approach. We also find evidence of degradation of the acids from exposure to a nonmonochromatic x‐ray source.

Thermal properties of perfluorinated n-alkanoic acids self-assembled on native aluminum oxide surfaces

We have examined the thermal and chemical properties of a homologous series of long-chain perfluorinated n-alkanoic acids [CF3(CF2)nCOOH, n=8, 10, 12, 14, 16] self-assembled on native aluminum oxide surfaces using thermal desorption mass spectrometry and monochromatic x-ray photoelectron spectroscopy. These monolayers were prepared by solution self-assembly under ambient conditions on pre-cleaned native aluminum oxide surfaces and then transferred into an ultrahigh vacuum environment for surface analyses. A chemisorption bond strength of ∼30 kcal/mol between the reactive acid head group and the native aluminum oxide surface has been derived from thermal desorption studies. Upon increasing surface temperature, the predominant surface process was found to be molecular desorption. In addition, a minor surface chemical reaction channel also coexists at elevated temperatures, resulting in thermal dissociation of the long chain acid molecules and subsequent formation of a partially fluorinated aluminum oxide su...

Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

Chemical oxide scaling by modulating ozone concentration is used to produce SiO/sub x/ interfaces with thickness as low as 0.3 nm for HfO/sub 2/ dielectrics. Poly NMOS capacitors and conventional self-aligned transistors down to 65 nm gate lengths with final EOT ranged from 1.2-1.8 nm were obtained. Sputtered TiN gate on the identical stacks yielded 0.82 nm EOT on NMOS devices using scaled chemical oxide interface with leakage current of 10/sup -3/ A/cm/sup -2/. CV hysteresis of TiN/HfO/sub 2/ was observed to decrease by an order of magnitude from the as deposited value to <10 mV after a 900/spl deg/C N/sub 2/ anneal.