P. Jannaty

Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator

We report on the fabrication and electrical characterization at room and low temperatures of a tunneling field-effect transistor (TFET). The devices are fabricated in thin germanium-on-insulator and consist of a heavily p+-doped, epitaxially grown source, a heavily n+-doped ion implanted drain, and a standard high-κ (HfO2) gate stack with an effective gate length Leff of 60 nm, obtained by trimming. The TFETs are fabricated using an ultralarge-scale integration compatible process flow. The devices exhibit an ambipolar behavior, reasonable on/off current ratio, and improved on current compared to silicon-on-insulator TFETs.

Axial SiGe Heteronanowire Tunneling Field-Effect Transistors

We present silicon-compatible trigated p-Ge/i-Si/n-Si axial heteronanowire tunneling field-effect transistors (TFETs), where on-state tunneling occurs in the Ge drain section, while off-state leakage is dominated by the Si junction in the source. Our TFETs have high I(ON) ~ 2 μA/μm, fully suppressed ambipolarity, and a subthreshold slope SS ~ 140 mV/decade over 4 decades of current with lowest SS ~ 50 mV/decade. Device operation in the tunneling mode is confirmed by three-dimensional TCAD simulation. Interestingly, in addition to the TFET mode, our devices work as standard nanowire FETs with a good I(ON)/I(OFF) ratio when the source-drain junction is forward-biased. The improved transport in both biasing modes confirms the benefits of utilizing bandgap engineered axial nanowires for enhancing device performance.

Full Two-Dimensional Markov Chain Analysis of Thermal Soft Errors in Subthreshold Nanoscale CMOS Devices

Thermally induced fluctuations in the logic state of a simple flip-flop occur on a timescale that renders them impossible to simulate through Monte Carlo methods. In a previous work, an analytical framework based on Markov chains and queue theory was introduced along with a symbolic solution for a truncated 1-D queue, diagonally connecting the two stable logic states in a two-dimensional (2-D) queue. In this paper, a complete solution for a full 2-D queue is presented, which maps all the possible thermal noise fluctuations of electron populations in flip-flop inverters. The results for the mean time to thermally induced error confirm the estimates given by truncated approximations. This formalism is also capable of computing arbitrary probability moments as well as steady-state distributions and transient behavior of the system. The full 2-D queue can also capture the statistics of other noise sources, like radiation-induced charge generation where the flip-flop can transiently reside in a queue state far from the diagonal connecting the two stable logic states of a flip-flop.

Growth, electrical rectification, and gate control in axial in situ doped p-n junction germanium nanowires

We report on vapor-liquid-solid growth and electrical properties of axial in situ doped p-n junction Ge sub-100 nm diameter nanowires. Room temperature four-point measurements show current rectification of two to three orders of magnitude depending on nanowire doping and diameter. We observe strong backgate control of reverse-bias current of up to three orders of magnitude and explain it by band-to-band tunneling modulated by the backgate-controlled electric field, as confirmed qualitatively via a quasi-three-dimensional Schrodinger–Poisson simulation.

Two-Dimensional Markov Chain Analysis of Radiation-Induced Soft Errors in Subthreshold Nanoscale CMOS Devices

Radiation-induced soft errors have been a reliability concern for logic integrated circuits since their emergence. Feature-size and supply-voltage reduction require the analysis of soft-error sensitivity as a function of technology scaling. In this paper, an analytical framework based on Markov chains and queue theory is presented for computation of alpha-particle-induced soft-error rates of a flip-flop operated in the subthreshold regime. The proposed framework is capable of reflecting the technology parameters such as supply voltage Vdd, channel length, process-induced threshold variation, and operating temperature. As an example, the framework is used to investigate the mean time to error of flip-flops built in a 32 nm fully-depleted silicon-on-insulator technology operating in the subthreshold regime subject to two limiting fluxes of alpha particle radiation: high at 100 (α/h.cm2) and ultra-low alpha (ULA) emission 0.002 (α/h.cm2).

Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS

In part I of this paper, a robust numerical framework based on Markov queueing theory and nonequilibrium Greens functions was presented to model the fluctuations in a CMOS flip-flop, which could potentially give rise to logic upsets. In part II, this framework is used to investigate quantitatively the failure in time for end-of-roadmap CMOS devices at the LG= 10 nm length scale as a function of various parameters such as size, temperature, threshold voltage, process-induced threshold variation, and VDD. It is shown quantitatively that process-induced variation and/or use of ultralow VDD make the devices extremely vulnerable to noise. Higher temperatures give rise to higher failure rates through increased thermal fluctuations and through reduced Ion/Ioff ratios, due to an inverse dependence of the subthreshold slope on temperature. The effect of nonlinear voltage-dependent node capacitors are modeled via the use of arbitrary-shaped queues, and the corresponding results are reported.

Shot-Noise-Induced Failure in Nanoscale Flip-Flops—Part I: Numerical Framework

As CMOS technology continues the path of miniaturization, noise-induced fluctuations raise heightened reliability concerns. In previous work, an analytical framework based on Markov queueing theory and Poisson shot noise was presented to model the probabilistic behavior of a CMOS flip-flop operated in the subthreshold regime. In this paper, this model is extended to also account for the above-threshold shot noise, where the noise distribution is no longer Poissonian. The formulas for the time-dependent charging and discharging of node capacitors of a four-transistor flip-flop are derived for different regimes of operation characterized by distinct Fano factors. The statistics of electron arrival and departure at node capacitors is incorporated in an algebraic representation based on Markov queueing theory to map the effects of charge fluctuations on the logic stability of a flip-flop. This framework is used in Part II of this work to investigate failure in time for end-of-roadmap CMOS at the 10-nm gate-length scale.

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices

Power consumption requirements drive CMOS scaling to ever lower supply voltages, reducing the stability margin with respect to thermal noise and raising the probability for thermally-induced soft errors. Given the long time scale of noise-induced soft errors, conventional Monte Carlo simulations cannot be used to predict error rates and alternative approaches are needed. In this paper, the analysis of thermal fluctuations in a CMOS flip-flop is performed using a 2D queue that maps the available configurations for the flip-flop in terms of electron populations on the two inverters, with the two stable logic states at the opposite corners of the 2D matrix. Trial simulations for model systems show that the thermally-induced logic transitions involve only a limited number of states immediately above and below the main diagonal of the full 2D queue. We present a numerical solution based on variable precision arithmetic for a truncated 2D queue consisting of a variable number of near-diagonal states. It is shown that increasing the width of the near-diagonal queue, an accurate solution for the error rate is asymptotically obtained without the need to consider the full 2D queue. Our approach is used to calculate the mean time to failure of flip-flops built in a 45-nm fully-depleted silicon-on-insulator (FD-SOI) technology modeled in the subthreshold regime, including parasitics. As a predictive tool, the framework can be used to investigate the thermal stability of devices built in future technologies and as a measure of device reliability in VLSI design.