R. I. Bahar

Designing logic circuits for probabilistic computation in the presence of noise

As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures confront devices and interconnections with a large number of inherent defects, which motivates the search for new architectural paradigms. In this paper, we examine probabilistic-based design methodologies for nanoscale computer architectures based on Markov random fields (MRF). The MRF approach can express arbitrary logic circuits and the logic operation is achieved by maximizing the probability of correct state configurations in the logic network depending on the interaction of neighboring circuit nodes. The computation proceeds via probabilistic propagation of states through the circuit. Crucially, the MRF logic can be implemented in modified CMOS-based circuitry that trades off circuit area and operation speed for the crucial fault tolerance and noise immunity. This paper builds on the recent demonstration that significant immunity to faulty individual devices or dynamically occurring signal errors can be achieved by the propagation of state probabilities over an MRF network. In particular, we are interested in CMOS-based circuits that work reliably at very low supply voltages (V/sup DD/ = 0.1-0.2 V), where standard CMOS would fail due to thermal and crosstalk noise, and transistor threshold variation. In this paper, we present results for simulated probabilistic test circuits for elementary logic components and well as small circuits taken from the MCNC91 benchmark suite and we show greatly improved noise immunity operating at very low V/sup DD/. The MRF framework extends to all levels of a design, where formally optimum probabilistic computation can be implemented as a natural element of the processing structure.

Designing Nanoscale Logic Circuits Based on Markov Random Fields

As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future is retaining high reliability in the presence of faulty devices and noise. Probabilistic computing offers one possible approach. In this paper we describe our approach for mapping circuits onto CMOS using principles of probabilistic computation. In particular, we demonstrate how Markov random field elements may be built in CMOS and used to design combinational circuits running at ultra low supply voltages. We show that with our new design strategy, circuits can operate in highly noisy conditions and provide superior noise immunity, at reduced power dissipation. If extended to more complex circuits, our approach could lead to a paradigm shift in computing architecture without abandoning the dominant silicon CMOS technology.

Thermally-induced soft errors in nanoscale CMOS circuits

Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit operation characterized by lower supply voltages VDD and smaller device sizes. Both of these downscaling approaches reduce the margin of immunity to thermal noise, alpha particle strikes, and threshold voltage variations. This paper investigates the noise probability distributions for both equilibrium and non-equilibrium logic states of advanced CMOS flip-flops operated at ultra-low VDD. The theoretical distribution of transition times from one stable operation point to the other stable operation point is also derived, which is a useful representation of the soft error rate. It is shown that such nanoscale flip-flop designs are extremely sensitive to threshold variations, reducing average failure time to a few days. Monte Carlo simulations are provided to validate the theoretical model and its predictions.

Designing MRF based Error Correcting Circuits for Memory Elements

As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementations of error correcting codes (ECC) can add to the reliability of systems but can be ineffective in highly noisy operating conditions. This paper proposes an implementation of ECC based on the theory of Markov random fields (MRF). The MRF probabilistic model is mapped onto CMOS circuitry, using feedback between transistors to reinforce the correct joint probability of valid logical states. We show that our MRF approach provides superior noise immunity for memory systems that operate under highly noisy conditions

Markov Chain Analysis of Thermally Induced Soft Errors in Subthreshold Nanoscale CMOS Circuits

The development of future nanoscale CMOS circuits, characterized by lower supply voltages and smaller dimensions, raises the question of logic stability of such devices with respect to electrical noise. This paper presents a theoretical framework that can be used to investigate the thermal noise probability distributions for equilibrium and nonequilibrium logic states of CMOS flip-flops operated at subthreshold voltages. Representing the investigated system as a 2-D queue, a symbolic solution is proposed for the moments of the probability density function for large queues where Monte Carlo and eigenvector methods cannot be used. The theoretical results are used to calculate the mean time to failure of flip-flops built in a current 45-nm silicon-on-insulator technology modeled in the subthreshold regime including parasitics. As a predictive tool, the framework is used to investigate the reliability of flip-flops built in a future technology described in the International Technology Roadmap for Semiconductors. Monte Carlo simulations and explicit symbolic calculations are used to validate the theoretical model and its predictions.

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits

Shrinking devices to nanoscale, increasing integration densities, and reducing voltage levels to the thermal limit-all conspire to produce faulty systems. A possible solution is a fault-tolerant probabilistic framework based on Markov random fields. This article introduces a new redundancy element, the MRF reinforcer, which achieves significant immunity to single-event upsets and noise

Enhancing online error detection through area-efficient multi-site implications

We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.

Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits

As CMOS technology downscales, higher noise levels, wider threshold variation, and low supply voltage will force designers to contend with high rates of soft logical errors and many defective devices. A probabilistic design framework based on Markov random fields (MRF) has been previously proposed to address dynamic fault and noise vulnerability of ultimate digital CMOS circuitry. The idea is to use additional transistors and feedback loops to achieve significant noise immunity and ensure correct logic operations at low VDD. However, the extra reliability achieved in previously published work came at a cost of high transistor counts. In this paper, the authors present techniques to reduce the transistor count of larger multilevel combinational circuits built within the MRF framework by using variable sharing, implied dependence and supergates. Using these techniques the authors show an average reduction of approximately 28% in transistor counts over a range of combinational benchmark circuits built within the MRF framework compared to the best previously published results

Accurate timing analysis using SAT and pattern-dependent delay models

Accurate delay modeling beyond static models is critical to garnering better correlation with post-silicon analysis. Furthermore, post-silicon timing validation requires a pattern-dependent timing model to generate patterns. To address these issues, a timing analysis tool was proposed that integrates a data-dependent delay model into its analysis. The approach solves for the delay by using the concept of circuit unrolling and formulation of timing questions as decision problems for input into a SAT solver. The effectiveness and validity of the proposed methodology is illustrated through experiments on benchmark circuits

Two-Dimensional Markov Chain Analysis of Radiation-Induced Soft Errors in Subthreshold Nanoscale CMOS Devices

Radiation-induced soft errors have been a reliability concern for logic integrated circuits since their emergence. Feature-size and supply-voltage reduction require the analysis of soft-error sensitivity as a function of technology scaling. In this paper, an analytical framework based on Markov chains and queue theory is presented for computation of alpha-particle-induced soft-error rates of a flip-flop operated in the subthreshold regime. The proposed framework is capable of reflecting the technology parameters such as supply voltage Vdd, channel length, process-induced threshold variation, and operating temperature. As an example, the framework is used to investigate the mean time to error of flip-flops built in a 32 nm fully-depleted silicon-on-insulator technology operating in the subthreshold regime subject to two limiting fluxes of alpha particle radiation: high at 100 (α/h.cm2) and ultra-low alpha (ULA) emission 0.002 (α/h.cm2).