P. Llinares

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

A 200 mm 0.35 /spl mu/m silicon-germanium heterojunction bipolar transistor (SiGe HBT) technology involving epitaxially-aligned polysilicon emitters is described. The devices are shown to combine the high speed performances typical for poly-Si emitter SiGe base devices (f/sub max/ up to 70 GHz) and the low 1/f noise properties of monocrystalline emitter structures (noise figure-of-merit KB as low as 7.2/spl times/10/sup -10/ /spl mu/m/sup 2/). Statistical current gain data are used to demonstrate the manufacturability of this innovative SiGe HBT technology.

Impact of grain number fluctuations in the MOS transistor gate on matching performance

This paper presents a compact model for the gate impact on MOS transistor matching. It is based on the random variations of grain number in the polycrystalline gate. The model is validated by fitting mismatch increase with substrate bias. This study highlights the importance of local polysilicon depletion and gives a better understanding of complex mechanisms that are responsible for MOSFET mismatch.

Low frequency noise characterization in 0.13 μm p-MOSFETs. Impact of scaled-down 0.25, 0.18 and 0.13 μm technologies on 1/f noise

Abstract This paper presents an experimental analysis of the noise measurements performed in 0.13 μm technology p-MOS transistors operating from weak to strong inversion in ohmic and saturation regimes. The 1/ f noise origin is interpreted in terms of carrier number with correlated mobility fluctuations. The contribution of the access resistance noise is noticed for large overdrive voltages. The slow oxide trap density N t ( E F ) and the Coulomb scattering noise parameter α s have been extracted. Then the 1/ f noise level in the three scaled-down p-MOSFETs generations (0.25, 0.18 and 0.13 μm) is compared. The variation of the noise parameter values is discussed with respect to the technology node. The highest oxide trap density is obtained for the thinnest gate oxide. It is concluded that the oxide thinning should lead to noise reduction only if the product t ox 2 . N t is taken into consideration. This trend will be significant in future scaled-down MOSFETs.

The impact of short channel and quantum effects on the MOS transistor mismatch

Abstract This paper presents the impact of short channel and quantum effects on the MOS transistor mismatch that become more and more important with the drastic reduction of device dimensions. For the first time, an analytical model is proposed for the MOSFET mismatch increase due to short channel effect. Besides, we demonstrate that the inversion layer quantization degrades transistor matching performance. The impact of quantum effect decreases with T ox , but its relative contribution is enlarged when the gate dielectric thickness is reduced.

1/f noise in 0.18 μm technology n-MOSFETs from subthreshold to saturation

Low frequency noise in 0.18 μm technology n-MOSFETs is investigated in subthreshold, ohmic and saturation regimes. The impact of the channel length on the drain current noise characteristics is studied. The results are analysed as a function of the drain current or gate voltage and compared to the existing noise models. We find that the 1/f noise can be interpreted in terms of carrier number fluctuations. The oxide trap density Nt at the Fermi energy level is evaluated. The significant deviation of the normalised noise amplitude observed at high VGS is attributed to the noise in the access resistances. In deep saturation regime, for gate length device <0.9 μm, the drain current spectral density tends to saturate with the gate overdrive voltage. The noise characteristics calculated with BSIM3v3 noise model are compared with the experimental results and discussed.

A new method for the channel-length extraction in MOSFETs with sub-2-nm gate oxide

A simple method to extract the effective channel length in deep-submicrometer devices with sub-2-nm gate oxide thickness is presented. The method uses the measured gate current from accumulation to strong inversion. It is easy to implement, fast, and accurate.

A new model for the current factor mismatch in the MOS transistor

Abstract This paper presents a new model for the current factor mismatch of the MOS transistor. It demonstrates that the impact of interface states is negligible. Therefore, the analytical model is based on the random variations of the dopant number in the channel region, similarly to V t mismatch model. As a result, the theoretical value of the matching parameter A β is 0.26%.μm for NMOS and 0.51%.μm for PMOS transistors that is close to experimental results.

A New Model for Threshold Voltage Mismatch Based on the Random Fluctuations of Dopant Number in the MOS Transistor Gate

Matching characterization is an important element in analog applications as it allows taking into account the electrical differences that occur between identically designed devices in circuit design and simulation. Moreover, it is becoming more and more important in developing the future technologies as matching parameters can be considered as a factor of merit in term of process maturity and performance. In the case of MOS transistors, it has been widely reported that mismatch is related to the random fluctuations of channel dopant number [1] [2] [3]. Then, the model based on the statistical fluctuations of dopant in the channel region predicts an area scaling law for threshold voltage fluctuations given by:

Dependence of Channel Width and Length on MOSFET Matching for 0.18 um CMOS Technology

Mismatch characterization has been performed on 0.18 μm CMOS technology for a wide range of dimensions for both N and P MOSFETs. It is the first time that a great number of dimensions has been tested : this allows to show the evolution of mismatch parameter AVt with both length and width. Matching degradation for short devices is related to the increase of effective channel doping level associated to the larger pocket influence. The effect of lateral isolation on the distribution of polysilicon grain size and orientation could explain mismatch decrease for narrow channel devices.

Comparison of low frequency noise and high frequency performances of double and simple polysilicon Bi-CMOS BJT

Abstract The issue of this paper concerns 0.35 μm Bi-CMOS double polysilicon bipolar transistors and 0.5 μm Bi-CMOS simple polysilicon bipolar transistors. Low-frequency noise measurements are performed. Noise spectral densities are analysed versus bias and geometry. From these noise measurements, base and emitter series resistances are extracted. A comparison of both technologies is done. Though double polysilicon transistors have a more complex structure than the simple polysilicon ones, they exhibit similar or even better performances. Indeed, DC characteristics and noise levels are equivalent for both technologies. Double polysilicon transistors exhibit a reduction of the base resistance and a significant improvement of the transition frequency f T is obtained.