G. Vincent

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

A 200 mm 0.35 /spl mu/m silicon-germanium heterojunction bipolar transistor (SiGe HBT) technology involving epitaxially-aligned polysilicon emitters is described. The devices are shown to combine the high speed performances typical for poly-Si emitter SiGe base devices (f/sub max/ up to 70 GHz) and the low 1/f noise properties of monocrystalline emitter structures (noise figure-of-merit KB as low as 7.2/spl times/10/sup -10/ /spl mu/m/sup 2/). Statistical current gain data are used to demonstrate the manufacturability of this innovative SiGe HBT technology.

New insights on the electronic properties of the trivalent silicon defects at oxidized 〈100〉 silicon surfaces

We perform a deep level transient spectroscopy (DLTS) measurement of the band‐gap energy distribution of the trivalent silicon defects (Pb centers) on as‐oxidized 〈100〉 silicon wafers. By comparison with the 〈111〉 silicon surface, we isolate the energy distribution of the Pb1 center. Its acceptor level is found at 0.42 ± 0.02 eV from the conduction band while the acceptor level for the 〈100〉 Pb0 center is found at 0.22 ± 0.01 eV, a value smaller than at the 〈111〉 surface (0.33 ± 0.01 eV). We obtain new results about the capture cross sections of the 〈100〉Pb centers by energy‐resolved DLTS trap filling experiments. The electron capture cross section of 〈100〉Pb1 is determined for the first time (5×10−16 cm2), while the electron capture cross section for 〈100〉 Pb0 (8×10−15 cm2) is found to be in agreement with earlier results.

Accurate measurements of capture cross sections of semiconductor insulator interface states by a trap‐filling experiment: The charge‐potential feedback effect

A measurement technique and analysis are presented for the accurate determination of the capture cross sections of the interface states in metal‐oxide‐semiconductor (MOS) structures. The technique utilizes the interface‐trap‐filling kinetics during measurements by energy‐resolved deep level transient spectroscopy (DLTS). High accuracy is attained by accounting in the analysis for the charge‐potential feedback effect which is a unique feature of the MOS structure and which presents a critical difficulty in the DLTS measurement of capture cross sections in MOS devices. The accurate measurement of the capture cross sections obtained in this work allows us to study several electronic properties of the Si‐SiO2 interface including (i) the behavior of the capture cross sections of interface states created by high‐field stress on MOS devices, and (ii) the determination of the capture cross section of dangling bonds at the 〈100〉‐oriented Si‐SiO2 interface. Finally, the possibility of determining the degeneracy fac...

Electrical determination of bandgap narrowing in bipolar transistors with epitaxial Si, epitaxial Si/sub 1-x/Ge/sub x/, and ion implanted bases

The apparent bandgap narrowing in bipolar transistors with epitaxial Si, epitaxial SiGe and ion implanted bases is measured from the temperature dependence of the collector current density J/sub c/(T). A graph of InJ/sub c/(T)/J/sub o/(T) as a function of reciprocal temperature is plotted, and the apparent bandgap narrowing obtained from the slope. For epitaxial base transistors, in which the boron base profiles are abrupt, a linear J/sub c/(T)/J/sub o/(T) characteristic is obtained, which allows the unambiguous determination of the apparent bandgap narrowing. The measured values for epitaxial Si bases are in good agreement with the theoretical model of Klaassen over a range of base doping concentrations. For Si/sub 0.88/Ge/sub 0.12/ and Si/sub 0.87/Ge/sub 0.13/ epitaxial base heterojunction bipolar transistors (HBTs), values of bandgap narrowing of 119 and 121 meV are obtained due to the presence of the Ge, which can be compared with theoretical values of 111 and 118 meV. For the implanted base transistor, the J/sub c/(T)/J/sub o/(T) characteristic is not linear, and its slope is larger at high temperatures than at low. This behaviour is explained by the presence of a tail on the ion implanted profile, which dominates the Gummel number of the transistor at low temperatures.

Metal oxide semiconductor structure and transistor behaviour using a single and simple graph (Qψ) which takes into account all the physical and electrical parameters

Physical properties and electrical characteristics of the metal oxide semiconductor (MOS) structure and the MOS transistor depend on numerous parameters: doping and permittivity of the semiconductor, thickness, permittivity and charge of the oxide, temperature, and, obviously, gate, drain, and substrate voltages. In this paper, we propose a single and simple graph to visualize and highlight the impact of all these physical and electrical parameters. All main classical relationships can be easily deduced from this graph, which is an additional efficient tool to understand MOS device behaviors.

Evaluation of transport properties of ozonized poly/mono interfaces in polysilicon emitter bipolar transistors

Abstract Temperature-dependent electrical measurements have been performed to determine hole and electron transport properties across the poly/mono interface in polysilicon emitter bipolar transistors. A tunneling probability has been extracted, and the results are correlated with noise parameters.

The Design and Fabrication of 0.35 µm Single-Polysilicon Self-Aligned Bipolar Transistors

Two innovative process technologies are introduced to overcome problems related to the downscaling of single-polysilicon self-aligned bipolar transistors. First, the use of a selective silicon deposition step before Ti salicidation of the structure is shown to improve TiSi2 formation on narrow As-doped polysilicon emitters. At the same time, the elevation of the extrinsic base regions around the emitter causes a significant reduction of peripheral electron recombination effects. Second, the implantation of the intrinsic base at a large tilt angle (LATIB) is demonstrated to suppress emitter-to-collector punchthrough along the isolation edges. The first 0.35 µm single-polysilicon self-aligned bipolar transistors fabricated using a 200 mm complementary metal oxide semiconductor (CMOS) derived bipolar process integrating these novel process technologies are described.

An investigation of polysilicon emitter bipolar transistors with an ozonized polysilicon/monosilicon interface

This paper reports the development of a new polysilicon/monosilicon interface preparation technique to adjust bipolar transistor properties. The interest of this new technique is demonstrated using physical characterizations, static and dynamic measurements on a 200mm 0.5μm BiCMOS technology. I) Introduction Oxygen at the poly/mono interface significantly affects the performances of poly emitter bipolar transistors. In particular, it is well known that an interfacial oxide layer increases the current gain and emitter resistance [1]. The aim of this paper is to evaluate new techniques for interfacial oxide formation. For the first time, a thin oxide layer has been introduced at the interface between in-situ doped emitter poly and Si using two different types of ozonization processes. We discuss the experimental results obtained on devices fabricated in a 200mm 0.5μm quasi self-aligned BiCMOS technology [2], and integrating an ozonized poly/mono interface. II) Interface preparation The use of ozone (O3) is advantageous for the combustion of possible hydrocarbon residues on the silicon surface and for its passivation and stabilization in time. In order to test different interfacial oxide thicknesses, two different ozone processes have been developed: i ) The first, HF + dry O3, corresponds to an O3 gaseous treatment after the well-known wet HF last clean. The interfacial oxide was obtained in the vapor phase cleaning module of an AST machine at room temperature under 100 hPa for 60sec, and its thickness is around 0.5-0.7nm as deduced from ellipsometric measurements [3]. i i ) The second, HF + wet O3, corresponds to a wet cleaning after the classical HF last, the O3 gas being diluted in water inside the CHAMBER FLOW machine before the deposition process. The equivalent oxide thickness (measured with a fixed refraction index of 1.465) of the interfacial layer is twice that of in the previous case (1nm). Diiodomethane contact angle measurements, which are sensitive to surface properties [4], suggest that in both cases, there is oxide growth (by analogy with reference thermal oxide) (Fig.1). As shown in Fig.1, the stability of the HF+dry O3 interface is similar to that of thermal oxide, while the HF+wet O3 changes more rapidly, as does the more conventional RCA prepared interface (Fig.2). The HF+dry O3 process thus appears to be a good choice for stable thin poly/mono interfacial oxide preparation, allowing a longer delay time before polysilicon emitter deposition. Fig.1: Diiodomethane contact angle evolution in time for thermal oxide,HF+dryO3, HF+wetO3 Fig.2: Diiodomethane contact angle evolution in time for RCA, HF+dryO3, HF+wetO3 III) Experimental results In our 0.5μm BiCMOS technology the emitter window is opened by dry etching in an oxide layer (800A thickness) (superposition of deposited oxide and thermal oxide). Immediately after the interface preparation (discussed above), the wafers were loaded in the in-situ doped polysilicon reactor. The total thermal budget was 850°C/15min + 1025°C/20sec for the investigated process which had been optimized earlier for an HF interface treatment. Several characterizations were performed after device fabrication: FIB-TEM-EELS, TEM, SIMS. Fig.3 shows EELS (Electron Energy Loss Spectroscopy) spectra recorded on the three different regions of the TEM cross-section shown in Fig.4. The integral of the signal, after background subtraction, provides a quantitative evaluation of the oxygen content (identified by the 530eV ionization threshold). The data show that there is indeed more oxygen at the interface (3%) than in the poly (0.7%) or in the monosilicon (0.5%). In addition, SIMS results show an increase in the interfacial oxygen dose after ozonization (Table 1), the largest oxygen dose being obtained for the wet O3 treatment. P ho to di od e C ou nt s Si poly 2K 500 550 600 Energy Loss (eV) 0,7% 500 550 600 Si mono 2K Energy Loss (eV) 0,5% P ho to di od e C ou nt s Interface 2K 4K 500 550 600 Energy Loss (eV) 3% P ho to di od e C ou nt s Ok

Suppression of boron transient-enhanced diffusion in SiGe HBTs by a buried carbon layer

The experiments described in this paper show that base broadening effects due to extrinsic base implantation in SiGe HBTs can be suppressed by introducing a buried carbon layer under the SiGe/Si base prior to epitaxy. They also demonstrate that SiGe HBTs with excellent static (/spl beta//spl times/V/sub AF//spl sim/10/sup 4/ V) and dynamic (f/sub T/B/spl times/BV/sub CEO//spl sim/200 GHz/spl times/V) characteristics can be fabricated using an epitaxially aligned in-situ-doped polysilicon emitter and an appropriately designed SiGe/Si base profile.

Static and Dynamic Characteristics of a 54 GHz fmax Implanted Base 0.35 µm Single-Polysilicon Bipolar Technology

High performance single-polysilicon npn bipolar transistors using a low cost 200 mm 0.35 µm bipolar technology have been fabricated, and the electrical properties related to physical and technological parameters. The devices feature record cut-off frequency and maximum oscillation frequency of 35 GHz and 54 GHz respectively, comparable to state-of-the-art results from more complex double-polysilicon bipolar processes.