P. Sakalas

Carbon Nanotube FET Technology for Radio-Frequency Electronics: State-of-the-Art Overview

Carbon-based electronics is an emerging field. Its present progress is largely dominated by the materials science community due to the many still existing materials-related obstacles for realizing practically competitive transistors. Compared to graphene, carbon nanotubes provide better properties for building field-effect transistors, and thus, have higher chances for eventually becoming a production technology.

Impact of pad and gate parasitics on small-signal and noise modeling of 0.35 /spl mu/m gate length MOS transistors

Microwave noise performance of p and n-type MOSFETs fabricated on the. same wafer was investigated in order to study the effect of the pad and gate parasitic circuit elements on noise performance. At low drain currents, the gate parasitic circuit was involved in the modeling to explain the observed kinks and loops in the s-parameters. Simulation of the noise parameters for p and n-type devices, measured in the 2-26 GHz frequency range, was performed by using extracted small-signal models of the transistor in connection with parasitic pad and gate circuits. Under the bias far from the optimal one, the additional parasitic inductance in the gate circuit was found responsible for the degradation of the noise performance by exhibiting peaks in the noise parameters.

Analog MMICs for millimeter-wave applications based on a commercial 0.14-/spl mu/m pHEMT technology

This paper describes recent results obtained from the monolithic-microwave integrated-circuit design activity at Chalmers University, Goteborg, Sweden. The goal is to design all circuits needed for the front end of a 60-GHz wireless local area network and to build various system demonstrators. Some recent experimental results from this activity like different 60-GHz amplifiers, a general-purpose IF amplifier, a 60-GHz resistive mixer, and frequency multipliers are reported in this paper. Parameters such as the gain, conversion loss, noise figure, dc-power dissipation, as well as the model used in the simulations are reported and discussed.

Systematic Compact Modeling of Correlated Noise in Bipolar Transistors

A systematic method for the integration of correlated shot-noise sources into compact models (CMs) is presented, which significantly improves the accuracy of predicted high-frequency noise in transistors. The developed method relies on a system theory approach, and hence, is not limited to specific CM or device type. In this paper, the method is applied to the CM HICUM, which serves a vehicle for verification purposes. The method and its implementation were verified for SiGe heterojunction bipolar transistors based on measured data for frequencies up to 50 GHz, as well as on device simulation data up to 500 GHz, obtained from simulations of both hydrodynamic and a Boltzmann transport model.

Experimental Investigation of RF Noise Performance Improvement in Graded-Channel MOSFETs

In this paper, measured RF noise performance of graded-channel metal-oxide-semiconductor (MOS) transistors (GCMOS - also named laterally asymmetric channel transistors) shows impressive reduction in minimum noise figure (NF min) as compared to classical MOSFET transistors (with the same gate length Lg = 0.5 mum). The reason is proven to be because of the higher noise correlation coefficient (C). GCMOS also shows lower sensitivity to extrinsic thermal noise as compared to classical MOSFET. Moreover, it is demonstrated that the use of 0.5- mum-gate-length GCMOS gives a competitive RF noise performance as compared to 0.25-mum-gate-length classical nMOS transistors.

Experiments on hot electron noise in semiconductor materials for high-speed devices

Experimental results on noise temperature and spectral density of current fluctuations (electron diffusion) at high electric fields in silicon, gallium arsenide, and indium phosphide are presented. The dominant noise sources are discussed in their relation to electron scattering mechanisms. Physical backgrounds of high speed-low noise performance (noise-speed tradeoff) are considered. Suppression in short samples of the fluctuations having long correlation time constant and (or) high threshold energy is discussed. >

CMOS Small-Signal and Thermal Noise Modeling at High Frequencies

In this paper, the behavior of radio frequency (RF) CMOS noise up to 24 GHz is analyzed and verified with measurements over a wide range of bias voltages and channel lengths. For the first time, approaches for excess noise factor modeling are validated versus measurements. Furthermore, important RF CMOS figures of merit are examined over many CMOS generations. With the scaling of CMOS technology, optimum RF performance is shown to be shifted from higher moderate toward lower moderate inversion, providing important guidelines for RFIC design. The results are validated with the charge-based EKV3 compact model, which considers short-channel effects such as channel length modulation, velocity saturation, and carrier heating.

Compact Modeling of High Frequency Correlated Noise in HBTs

A compact model solution, consistent with the system theory for correlated base and collector shot noise sources, is derived and implemented in the bipolar transistor model HICUM using Verilog-A. Compiled (with Tiburon) Verilog-A model is simulated using ADS 2004A and the results are tested against measured noise parameters for high-frequency (fT at 150 GHz) SiGe HBTs. Very good agreement between simulated and measured data is obtained

High frequency noise in manufacturable carbon nanotube transistors

HF noise parameters were measured and modeled for the first time for wafer-scale manufacturable CNTFETs. These first multi-tube multi-finger CNTFETs exhibit still relatively high values for the minimum noise figure (NFmin = 3.5 dB at 1 GHz). Based on detailed compact modeling, the origin of this noise can be explained by the existence of the parasitic network and metallic tubes.

A Semiphysical Large-Signal Compact Carbon Nanotube FET Model for Analog RF Applications

A compact large-signal model, called Compact Carbon Nanotube Model (CCAM), is presented that accurately describes the shape of DC and small-signal characteristics of fabricated carbon nano-tube FETs (CNTFETs). The new model consists of computationally efficient and smooth current and charge formulations. The model allows, for a given gate length, geometry scaling from single-finger single-tube to multifinger multitube transistors. Ambipolar transport, temperature dependence with self-heating, noise, and a simple trap model have also been included. The new model shows excellent agreement with the data from both the Boltzmann transport equation and measurements of Schottky-barrier CNTFETs and has been implemented in Verilog-A, making it widely available across circuit simulators.