Tobias Nardmann

A Geometry Scalable Approach to InP HBT Compact Modeling for mm-Wave Applications

The bias and frequency dependent scaling of InP/InGaAs HBTs with emitter width (and length) has been investigated for a 300GHz foundry process. It was found that the currents, capacitances and resistances related to the emitter dimensions scale quite well. This allows the use of special test structures in combination with geometry variations to distinguish different physical effects and to accurately determine the external elements of the transistor as well as the thermal resistance independently of each other. The approach enables the generation of a geometry scalable set of HICUM/L2 model parameters for a large geometry range. The model was compared to experimental DC, AC and large-signal data of devices with different emitter geometry. The good agreement offers a much wider range of options for optimizing high-speed InP circuits.

Energy-Efficient Transceivers for Ultra-Highspeed Computer Board-to-Board Communication

Enabling the vast computational and throughput requirements of future high performance computer systems and data centers requires innovative approaches. In this paper, we will focus on the communication between computer boards. One alternative to the bottleneck presented by copper wire based cable-bound communication is the deployment of wireless links between nodes consisting of processors and memory on different boards in a system. In this paper, we present an interdisciplinary approach that targets an integrated wireless transceiver for short-range ultra-high speed computer board-to-board communication. Based on our achieved results and current developments, we will also estimate energy consumption of such a transceiver.

An evaluation of extraction methods for the emitter resistance for InP DHBTs

The emitter series resistance is a very important parameter for bipolar transistors since it can have a significant impact on both the DC and high-frequency characteristics of transistors. Its accurate determination is quite difficult due to the complicated emitter material stack and the lack of suitable test structures. Thus, extraction methods that rely on transistor terminal characteristics must be used instead. In this paper, the accuracy of several widely used extraction methods for the emitter resistance has been investigated for three different type I InP DHBT technologies by applying the methods to both measured and simulated data. Since for the latter the emitter resistance is exactly known, it allows a reliable evaluation of the accuracy and the applicability of a method.

Electrical Characterization of Emerging Transistor Technologies: Issues and Challenges

Experimental results gained by various electrical characterization techniques are discussed and compared for a CNTFET technology, which suffers as almost all emerging technologies from traps in the gate oxide. Based on these results, it is highlighted that, contrary to common practice, a fast data acquisition technique is required to ensure a proper electrical device characterization in terms of 1) trap-free device characteristics, 2) reproducible experimental results, and 3) a consistent set of dc and small-signal (ac) characteristics. It is argued that a reasonable technology comparison among emerging technologies must be based on data fulfilling these criteria since trap-affected measurements distort the device behavior which can lead to wrong conclusions about the performance of a device such as the apparent linearity. A trap model capturing the aforementioned issues is briefly introduced. Moreover, the challenges of the electrical characterization of high-impedance devices are explored.

A length-scalable compact model for InP DHBTs

A parameter set for a modified HICUM/Level0 compact model has been extracted for an InP DHBT production technology. The parameters can be scaled to describe devices of different emitter lengths very well by using simple scaling equations. This indicates that major elements of the equivalent circuit are estimated correctly and is the first step towards a fully scalable compact model for a InP HBT technology.

SiGeC and InP HBT Compact Modeling for mm-Wave and THz Applications

An overview on compact transistor modeling for mm-wave HBT technologies is provided. Using HICUM as a vehicle, a comparison to experimental DC, AC and large-signal data is performed. Selected examples are shown for advanced SiGeC and InP HBTs with operating frequencies (fT, fmax) of (300, 500) GHz and (350, 450) GHz, respectively. Good agreement between model and measurements is obtained for all characteristics

Microwave Noise Analysis in InP and GaAs HBTs

High frequency (h.f.) noise characteristics of advanced InP and GaAs HBTs were measured and simulated. The compact model (CM) HICUM/L2 v2.34 was used for the DC, AC and noise simulation as well as for the noise analysis. Geometry scalable model parameters for InP HBTs with the different emitter widths and lengths were extracted from temperature dependent DC and AC measurements on HBTs and special test structures. The CM is in good agreement with measured data. Non-equilibrium electron transport was found to shape fT and fmax for GaAs HBTs. For both HBT types, based on the noise source decomposition, an analysis of the influence of the different noise sources on the minimum noise figure (NFmin) was performed at different base-collector biases VBC. It was found that noise due to intervalley transfer related electron scattering has negligible impact on NFmin for both InP and GaAs HBTs. H.f. noise reduction as a result of Coulomb current blocking in GaAs HBTs was confirmed. Shot noise correlation was investigated in GaAs HBTs with different base layer thickness (wB) and base doping for the optimal h.f. noise behavior.

A Multiregion Approach to Modeling the Base-Collector Junction Capacitance

The junction capacitance of heterojunction bipolar transistors (HBTs) is commonly modeled based on the theory of the p-n-homojunction with constant doping levels, made more flexible by the introduction of adjustable model parameters. In III-V HBTs, however, the low-doped collector is often not uniform, but contains both material and doping steps used to suppress the collector current blocking and to improve the linearity. Under these circumstances, the classical formulation is not sufficient to model the capacitance. Similarly, the exponential spatial doping dependence in the collector of modern high-speed HBTs may require a more in-depth approach. In this brief, a smooth expression for modeling the junction capacitance of a multiregion layer stack is presented. The accuracy of the new model is demonstrated based on both simulated and measured data.

Harmonic distortion analysis of InP HBTs with 650 GHz f max for high data rate communication systems

High frequency (h.f.) harmonic distortion (HD) of advanced InP heterojunction bipolar transistors (HBTs) with various emitter widths was investigated. Geometry scalable parameters for the compact model (CM) HICUM/L2 v. 2.34, featuring a two-region base-collector capacitance formulation, were extracted from temperature dependent DC and AC measurements of HBTs and from the special test structures. Single tone harmonic distortion and active two tone load pull measurements were carried out for different emitter area devices. The compact model was used for data analysis.

A Closed-Form Solution for the Low-Current Collector Transit Time in Group IV and Group III-V HBTs

In certain types of heterojunction bipolar transistors (HBTs), the carrier transit time associated with the base-collector (BC) space-charge region constitutes a significant contribution to the total transit time. In many compact models, the low-current BC transit time is lumped in with the total low-current transit time and often assumed to be constant—dependent only on the collector width and material saturation velocity. This assumption, however, is insufficient for modeling high-voltage Si-based HBTs as well as for III-V HBTs, where the negative differential mobility (NDM) effect can become relevant in high-speed low-power circuits. This paper presents a closed-form solution for the low-current collector transit time based on a novel accurate analytical velocity-field formulation, covering both group IV and group III-V semiconductor materials. The new solution includes the NDM effect and is suitable for implementation in compact models, and its relevance and accuracy are demonstrated for both TCAD simulated and measured data.