P. Shah

High density contactless, self aligned EPROM cell array technology

A revolutionary EPROM cell technology has been developed. Its suitability to realize high density memories with performance and reIiability comparable to the conventional EPROMS has been demonstrated with a 64K bit density vehicle. This self-aligned contactless cell is in a crosspoint array configuration, and occupies 33 percent less area than a conventional cell at comparable design rules. The planar, contactless technology has enhanced manufacturability, scalability and is ideally suited for memories beyond megabit density.

An experimental 4 Mb flash EEPROM with sector erase

A 512K*8 flash EEPROM (electrically erasable programmable ROM) which operates from a single 5-V supply was designed and fabricated. A double-poly, single-metal CMOS process with a minimum feature size of 0.9 mu m was developed to manufacture the test vehicle, which resulted in a die size of 95 mm/sup 2/. The storage cell is 8.64 mu m/sup 2/ and consists of a one-transistor cell that uses a remote, scalable, tunnel diode for programming and erasing by Fowler-Nordheim tunneling. Process high-voltage requirements are relaxed by utilizing circuit techniques to alleviate the burden of high voltages. A segmented architecture provides the flexibility to erase any one sector (16 kB) or the entire chip during one cycle by an erase algorithm. The memory can be programmed one byte at a time, or the internal bit-line latches can be used to program a 256-B page in one cycle. A programming time of 10 ms is typical, which results in a write time of 40 mu s/B during page programming. The chip features an access time of 90 ns. >

A new technique for determining the capacitive coupling coefficients in flash EPROMs

A method for determining the capacitive coupling coefficients of flash erasable programmable read only memories (EPROMs) is introduced. This technique relies on the Fowler-Nordheim erase measurements and source/drain junction leakage characteristics of the device to extract the control gate, source, and drain coupling coefficients. An advantage offered by this method is its use of an actual flash EPROM cell without requiring additional test structures.<<ETX>>

Optimization of a source-side-injection FAMOS cell for flash EPROM applications

A 0.6- mu m FAMOS cell structure, which features a lightly doped source region to achieve enhanced source-side-injection for channel hot electron programming, is presented. The use of the source-side-injection mechanism for EPROM programming has been previously proposed, but this work is the first time that a source-side-injection cell with a lightly doped source region has been fabricated and evaluated. The impact of the source dopant concentration and the depth of this non-overlapped LDD (lightly doped drain) region on cell programming performance has been characterized and optimized. The optimized cells exhibit excellent programmability for drain voltage down to 3.3 V. Studies of reliability issues and write/erase endurance results indicate that this cell is a viable candidate for 5-V, or 3.3-V, high-density flash EPROM applications.<<ETX>>

A 5-volt contactless array 256 kbit flash EEPROM technology

A contactless cell array technology has been developed for a single-power-supply 5V-only CMOS flash EEPROM (electrically erasable programmable read-only memory). The technologys suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM test vehicle. This low-current approach has been realized with cell area and cost comparable to those of the recently reported dual-power-supply flash EEPROMs.<<ETX>>

High performance, high density MOS process using polyimide interlevel insulation

High performance, high density scaled MOS processes have been developed by reducing parasitic lead capacitances and resistances through the use of MoSi2gates and polyimide as interlevel dielectric insulator. The self-aligned gates were passivated using dual layer of doped oxide and DuPont PI2545 polyamic resin 1.7 micron thick reducing interlevel capacitance to 2.66×10-9farads/cm2, half that of conventional doped oxide. The speed power products estimated from 25 stage ring oscillator with 2 micron gates on 600Å gate oxides show minimum delays of 500 psec/gate and minimum speed power product of 120 femto joules at lower currents.

A novel sublithographic tunnel diode based 5V-only flash memory

A novel tunnel diode has been developed for high-density 5-V-only flash memories. The memory tunnel diode is remote from the channel, self-aligned, sublithographic, and scalable. This remote tunnel diode provides several advantages over a conventional tunnel diode: higher junction breakdown voltage, reduced substrate current during erase, reduced tunnel oxide area, reduced cell area, and competitive cell endurance. A 256-kb 5-V-only flash memory incorporating this tunnel diode is shown to have excellent operation and reliability characteristics.<<ETX>>

A 5 V-only 256 kbit CMOS flash EEPROM

The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized.<<ETX>>

Chapter 4 - Ultrathin-Gate Dielectric Processes for VLSI Applications

Publisher Summary This chapter describes ultrathin-gate dielectric processes for very large scale integration (VLSI) applications. It discusses the methods for growing thin oxides in the sub-200-A range and also describes the electrical characteristics of these films. The standard manufacturing process for gate oxides has been a 1000°C, dry O2 process with a small amount of HCl added. The amount of HCl added is less than 6%, and its purpose is to neutralize any mobile ionic contamination that may be introduced into the oxide, such as sodium. The oxidation is followed with a high-temperature anneal in an inert ambient, such as argon or nitrogen. High-quality oxides can also be grown with a similar process but with steam replacing the dry O2. The advantage with this technique is that large differential growth rates are obtained between single-crystal substrates and polysilicon layers. This differential is exploited in the manufacture of circuits such as dynamic random access memories.

Analysis of vertical multijunction solar cells using a distributed circuit model

Abstract Vertical multijunction (VMJ) solar cells have generated considerable interest due to their improved performance in terms of conversion efficiency and radiation tolerance compared to the conventional planar solar cells. Fabrication of VMJ cells with junction density of 2000 junctions/cm is now possible using advanced fabrication technologies. This work describes an analysis of some of the VMJ cell structures now being fabricated—especially the ones that combine the enhanced red response and radiation tolerance of the VMJ concept and blue response of conventional planar cells. A distributed equivalent circuit model is used for analysis of complicated junction configurations—which otherwise would be very cumbersome using conventional carrier transport equations. The VMJ cell structures were analyzed to study their device characteristics and their sensitivity to various material and fabrication parameters such as epitaxial layer resistivity and carrier lifetimes. The results show that the conversion efficiency is higher than conventional devices due to efficient carrier collection with a superior radiation tolerance. The cells, however, degrade more rapidly compared to planar cells at higher radiation levels determined by the structural parameters.