P. Sheldon

Fabrication procedures and process sensitivities for CdS/CdTe solar cells

This paper details the laboratory processes used to fabricate CdS/CdTe solar cells at the National Renewable Energy Laboratory. The basic fabrication technique includes low-pressure chemical vapor deposited SnO2 , chemical-bath deposited CdS, close-spaced sublimated CdTe, solution-CdCl2 treatment, and an acid-contact etch, followed by application of a doped-graphite paste. This paper also describes the results of a reproducibility study in which cells were produced by multiple operators with an average AM1·5 efficiency of 12·6%. And finally, this paper discusses process sensitivities and alternative cell fabrication procedures and reports the fabrication of a cell with an AM1·5 efficiency of 15·4%. Copyright

Time-resolved photoluminescence studies of CdTe solar cells

We show that time-resolved photoluminescence measurements of completed polycrystalline CdTe solar cells provide a measure of recombination near the CdTe/CdS metallurgical interface that is strongly correlated to the open-circuit voltage in spite of complex carrier dynamics in the junction region. Oxygen in the growth ambient during close-spaced sublimation generally reduces this recombination rate; grain size does not have a strong effect.

Interdiffusion of CdS and Zn2SnO4 layers and its application in CdS/CdTe polycrystalline thin-film solar cells

In this work, we found that the interdiffusion of the CdS and Zn2SnO4 (ZTO) layers can occur either at high temperature (550–650 °C) in Ar or at lower temperature (400–420 °C) in a CdCl2 atmosphere. By integrating a Zn2SnO4 film into a CdS/CdTe solar cell as a buffer layer, this interdiffusion feature can solve several critical issues and improve device performance and reproducibility of both SnO2-based and Cd2SnO4-based CdTe cells. Interdiffusion consumes the CdS film from both the ZTO and CdTe sides during the device fabrication process and improves quantum efficiency at short wavelengths. The ZTO film acts as a Zn source to alloy with the CdS film, which results in increases in the band gap of the window layer and in short-circuit current density Jsc. Interdiffusion can also significantly improve device adhesion after CdCl2 treatment, thus providing much greater process latitude when optimizing the CdCl2 process step. The optimum CdCl2-treated CdTe device has high quantum efficiency at long wavelength,...

Dislocation density reduction through annihilation in lattice‐mismatched semiconductors grown by molecular‐beam epitaxy

Epitaxial InAs/GaAs, GaAs/Ge/Si, GaAs/InP, and InAs/InP heterostructures are grown by molecular‐beam epitaxy. Transmission electron microscopy studies reveal that, for these heteroepitaxial systems, the threading dislocation density is inversely proportional to the epilayer thickness. At a given thickness, the threading dislocation density is relatively insensitive to lattice mismatch (3.2%<‖Δa‖/a<7.2%), to differences in thermal expansion coefficients (6.9×10−7<‖Δα‖<3.4×10−6 K−1), to interfacial surface chemistry, and to epilayer morphology. Epitaxial layers incorporating growth interrupts produce lower overall defect densities, yet they maintain defect‐reduction profiles similar to those observed in layers without the growth interrupt.

Intermixing at the CdS/CdTe Interface and its Effect on Device Performance

A study of the CdS/CdTe interface was performed on glass/SnO 2 /CdS/CdTe device structures. CdS layers were deposited by chemical solution growth to a thickness of 80–100 nm, and CdTe was deposited by close-spaced sublimation at substrate temperatures of 500°, 550°, and 600°C. Post-deposition CdCl 2 heat treatment was performed at 400°C. Samples were analyzed by optical spectroscopy, secondary ion mass spectrometry (SIMS), spectral response, and current-voltage measurements. SIMS analysis shows that the intermixing of CdS and CdTe is a function of substrate temperature and post-deposition CdCl 2 heat treatment. The degree of intermixing increases with increases in substrate temperature and the intensity of CdCl 2 heat treatment. Optical analysis and X-Ray diffraction data show that the phases of CdS x Te 1-x are also a function of the same parameters. Formation of a Te-rich CdS x Te 1-x alloy is favored for films deposited at higher substrate temperatures. Spectral response of the devices is affected by the degree of alloying at the interface. The degree of alloying is indicated by simultaneous changes in long wavelength response (due to the formation of lower bandgap intermixed CdS x Te 1-x ) and the short wavelength response (due to the change in CdS thickness). Device performance is heavily influenced by alloying at the interface. With optimized intermixing, improvements in V oc , and diode quality factors are observed in the resulting devices.

Determination of Cu in CdTe/CdS devices before and after accelerated stress testing

The distribution of Cu before and after accelerated stress testing of high-efficiency CdTe/CdS solar cells has been studied using high mass resolution secondary ion mass spectrometry (SIMS). Standard high-efficiency CdTe/CdS devices were used in this work. Back contacts were graphite paste with varying amounts of Cu added in the form of HgTe:Cu powder. The contacts were applied to the devices after back-surface treatment (NP etch). In one device, no intentional Cu was added to the graphite paste. The devices were stressed at open-circuit voltage in light and at 100/spl deg/C for /spl sim/1000 hours. SIMS depth profiles were performed on devices after stressing and also on companion devices that were not stressed. The stressed devices show an accumulation of Cu in the CdS layer. Copper levels in the CdS are correlated with the amount of Cu in the graphite paste contact, with higher Cu in the contact resulting in more Cu in the CdS. The Cu level in the CdTe layer is shown to be relatively constant for all devices. The Cu levels in these devices are quantified to provide absolute concentrations.

Influence of CdS/CdTe interface properties on the device properties

In this paper, the authors have focused on the formation and the role of the CdS/CdTe interface on CdTe solar cells. The devices were made using chemical bath deposited (CBD) CdS on SnO/sub 2//glass substrates and the CdTe was deposited by close spaced sublimation (CSS) and subsequently CdCl/sub 2/ treated and annealed. Compositional analysis showed considerable interdiffusion of Te and S as well as Cl accumulation at the interface. Micro-photoluminescence (PL) analysis reveals sulfur accumulation at the grain boundaries and a graded CdS/sub x/Te/sub 1-x/ alloy at the interface. Their analysis leads them to conclude that Cl accumulation and anion vacancies result in a one sided n/sup +/-p junction. This model could explain the collection loss in the CdS layer, seen in the spectral response of CdS/CdTe devices.

CdS/CdTe thin-film solar cell with a zinc stannate buffer layer

This paper describes an improved CdS/CdTe polycrystalline thin-film solar-cell device structure that integrates a zinc stannate (Zn2SnO4 or ZTO) buffer layer between the transparent conductive oxide (TCO) layer and the CdS window layer. Zinc stannate films have a high bandgap, high transmittance, low absorptance, and low surface roughness. In addition, these films are chemically stable and exhibit higher resistivities that are roughly matched to that of the CdS window layer in the device structure. Preliminary device results have demonstrated that by integrating a ZTO buffer layer in both SnO2-based and Cd2SnO4 (CTO)-based CdS/CdTe devices, performance and reproducibility can be significantly enhanced.

High-efficiency Cd/sub 2/SnO/sub 4//Zn/sub 2/SnO/sub 4//Zn/sub x/Cd/sub 1-x/S/CdS/CdTe polycrystalline thin-film solar cells

CdTe-based thin-film solar cells have been limited to the conventional SnO/sub 2//CdS/CdTe device structure. In this paper, we report a modified device structure consisting of Cd/sub 2/SnO/sub 4//Zn/sub 2/SnO/sub 4//Zn/sub x/Cd/sub 1-x/S/CdS/CdTe layers, that yields improved performance and reproducibility. Cadmium stannate (Cd/sub 2/SnO/sub 4/, or CTO) transparent conductive oxide (TCO) films have several significant advantages over conventional SnO/sub 2/ films. CTO-based CdTe cells have approximately 1 mA/cm/sup 2/ higher J/sub sc/ than SnO/sub 2/-based CdTe cells. Integrating zinc stannate (Zn/sub 2/SnO/sub 4/, or ZTO) into the device as a buffer layer helps maintain high V/sub oc/ and fill factor when reducing CdS thickness to improve J/sub sc/. XPS and SIMS results show substantial interdiffusion between the CdS and ZTO layers. This feature can be used to optimize device performance and reproducibility. We have fabricated a Cd/sub 2/SnO/sub 4//Zn/sub 2/SnO/sub 4//Zn/sub x/Cd/sub 1-x/S/CdS/CdTe cell with an NREL-confirmed total-area efficiency of 15.8%.

The effect of high-resistance SnO2 on CdS/CdTe device performance

In this paper, we have studied the effect of high-resistance SnO2 buffer layers, deposited by low-pressure chemical-vapor deposition, on CdS/CdTe device performance. Our results indicate that when CdS/CdTe devices have a very thin layer of CdS or no CdS at all, the i-SnO2 buffer layer helps to increase device efficiency. When the CdS layer is thicker than 600{angstrom}, the device performance is dominated by CdS thickness, not the i-SnO2 layer. If a very thin CdS layer is to be used to enhance device performance, we conclude that a better SnO2 buffer layer is needed.