P. Spirito

Silicon electro-optic modulator based on a three terminal device integrated in a low-loss single-mode SOI waveguide

We analyze, from a theoretical point of view, a novel silicon optical amplitude-phase modulator integrated into a SOI (silicon on insulator) optical waveguide and based on a three terminal electronic structure which gives rise to definite advantages in comparison with a classical p-i-n diode based modulator. The proposed device utilizes the free carrier dispersion effect to produce the desired refractive index and absorption coefficient variations. The MEDICI two-dimensional (2-D) semiconductor device simulator has been used to analyze the electrical operation, with reference to the free carrier concentration injected into the optical channel, its uniformity and the required current density and electrical power. The optical investigation was carried out by means of FDM (finite difference method), EIM (effective index method), and BPM (beam propagation method) tools, giving rise to a complete evaluation of the properties of our device. We report the results for both the amplitude and phase modulators, paying attention to the static and the dynamic behavior. In particular, an amplitude modulation of 20%, with an injection power of about 126 mW, and a switching time of 5.6 ns can be achieved theoretically, Furthermore, as a phase modulator, the device exhibits a very high figure of merit, predicting an induced phase shift per volt per millimeter of about 215/spl deg/, for a injection power of about 43 mW, and a switching time shorter than 3.5 ns.

AN ELECTRICALLY CONTROLLED BRAGG REFLECTOR INTEGRATED IN A RIB SILICON ON INSULATOR WAVEGUIDE

In this letter, we present a novel structure for light amplitude modulation based on a lateral p-i-n diode combined with a Bragg reflector which transforms the phase shift induced by the plasma dispersion effect in the intrinsic region of the diode into a voltage controlled variation of the reflectivity of the Bragg mirror. Numerical simulations show a modulation depth of 50% achieved in about 12 ns with a power dissipation of 4.0 mW and an insertion loss of 1.0 dB. The device is demonstrated to be very attractive in terms of power dissipation as compared to a Mach–Zehnder interferometer occupying the same area on chip.

A quasi-one-dimensional analysis of vertical JFET devices operated in the bipolar mode

Abstract “Bipolar operation”, namely forward-basing the gate-source diode of a JFET, has been proposed in the literature as a means to reduce the on-state resistance of such devices. In this paper, the physics of bipolar operation of power JFETs is analysed in detail and closed-form solutions of its output characteristics are derived as a function of the device geometry and of physical parameters of the semiconductor. From that model, it turns out that the low value of the saturation voltage originates from the existence of an high-density electron-hole plasma that fills the space between source and drain. In the active region of the output characteristics, the control of the gate current the drain current is due to the possibility to control the level of majority-carrier injection from the source transition. The closed-form expression for the current gain allows to identify the structure parameters that affect it. It shown that, under suitable conditions, a substantial current amplification can be observed. The model has been found to be in good agreement with the results obtained on experimental devices.

Performance analysis of a bipolar mode FET (BMFET) with normally off characteristics

The fabrication and the characterization of a family of power Bipolar Mode JFETs (BMFET) is reported. In these devices, blocking voltages up to 1000 V or currents up to 18 A (corresponding to 800 A/cm2) have been obtained. Results allow to get an insight in the physics of operation of the BMFET, to define their theoretical limits of operation, and to understand the reasons for the superior performance of the present device, with respect to the Bipolar Transistor.

Experimental Detection and Numerical Validation of Different Failure Mechanisms in IGBTs During Unclamped Inductive Switching

The physics of the different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in punchthrough (PT) and not PT (NPT) insulated-gate bipolar transistor (IGBT) structures is analyzed in this paper. Both 3-D electrothermal numerical simulations and experimental evaluations support the theoretical analysis. Experimental results for UIS test show that, at low time duration (or inductance value) of the test, the UIS limit moves from energy limitation to current limitation. While the energy limitation is well known, the current-limited failures are less studied. In this paper, the current limit for UIS test is analyzed in detail, and the cause is attributed to a filamentary current conduction due to the presence of a negative differential resistance (NDR) region in the IC- VCE curve in breakdown. The filamentary current conduction locally increases the current density causing early device latch-up and possible device failure at a current much lower than the one dictated by energy limitations. The physical parameters that affect both the onset of NDR region and the failure current are discussed for both an NPT trench IGBT structure with a local lifetime control and a PT trench IGBT structure with a field-stop layer.

Analytical model for thermal instability of low voltage power MOS and SOA in pulse operation

Thermal instability presented by some high current power MOS has been shown to limit significantly the SOA capability. In this paper, we present a new analytical model to explain this type of instability in transient operation, based on an analytical formulation for both the positive temperature coefficient of the drain current and for the thermal resistance. The model is capable of predicting the onset of thermal instability for a given device structure and layout, and can be used both to define the allowed SOA of the device and as a design guide to design more rugged devices.

Thermal instabilities in high current power MOS devices: experimental evidence, electro-thermal simulations and analytical modeling

The phenomenon of the thermal instability presented by some high current power MOS has been intensively investigated, both by experimental means and by numerical simulations. An analytical expression for the positive temperature coefficient of the Drain current has been developed and a model for the thermal instability in transient operation has been proposed. The results explain the main causes of the thermal instability and give some rules to evaluate the possible failure occurrence for a given device.

High-voltage bipolar mode JFET with normally off characteristics

The first realization of a power vertical JFET operated in the bipolar mode (BJFET) with normally off behavior is reported. The structure combines minority carrier injection from the gate region in the on-state, and lateral pinch-off of the channel, due to the built-in voltage, in the off-state. The realized devices show high blocking voltages, up to 900 V, with zero gate bias, and have extremely low on-resistance. Fast switching speeds with forced gate turn-off times as low as 100 ns for devices of 600-V blocking voltages have been obtained.

Numerical analysis of local lifetime control for high-speed low-loss P-i-N diode design

The effect of localized lifetime control technique on the static and dynamic behavior of a power P-i-N diode is investigated in this paper. Mixed mode device circuit simulations are used in order to analyze the effect of the width and position of a reduced lifetime region on the diode. The simulations show that the optimal position for the low-lifetime region is at the beginning of the base region on the anode side, while the optimal width of the low-lifetime region depends on the amount of lifetime reduction. The local lifetime control design technique is shown to be effective in reducing the turn-off time and increasing diode softness with a little worsening of on-state voltage drop. It is shown that the tradeoff curve obtained by diodes using local lifetime control is better than the one achieved with lifetime killing in the whole epilayer region.

Negative resistance induced by avalanche injection in bulk semiconductors

The negative resistance induced by space-charge effects in bulk semiconductor devices subjected to avalanche multiplication has been studied to clarify the physics of this phenomenon and the validity of the assumptions made by other authors. On the basis of the numerical results, an analytical model is proposed, using the regional approximation to evaluate the field along the device and the J-V characteristic. Both the numerical and the analytical results show the role played by the injection of electrons from the cathode and the velocity saturation for the onset of negative resistance, as well as the role of hole injection from the multiplication region near the anode into the bulk for the subsequent voltage lowering. Experimental results are in good agreement with the analytical model in a wide range of device parameters.