Gianfranco Vitale

A quasi-one-dimensional analysis of vertical JFET devices operated in the bipolar mode

Abstract “Bipolar operation”, namely forward-basing the gate-source diode of a JFET, has been proposed in the literature as a means to reduce the on-state resistance of such devices. In this paper, the physics of bipolar operation of power JFETs is analysed in detail and closed-form solutions of its output characteristics are derived as a function of the device geometry and of physical parameters of the semiconductor. From that model, it turns out that the low value of the saturation voltage originates from the existence of an high-density electron-hole plasma that fills the space between source and drain. In the active region of the output characteristics, the control of the gate current the drain current is due to the possibility to control the level of majority-carrier injection from the source transition. The closed-form expression for the current gain allows to identify the structure parameters that affect it. It shown that, under suitable conditions, a substantial current amplification can be observed. The model has been found to be in good agreement with the results obtained on experimental devices.

Performance analysis of a bipolar mode FET (BMFET) with normally off characteristics

The fabrication and the characterization of a family of power Bipolar Mode JFETs (BMFET) is reported. In these devices, blocking voltages up to 1000 V or currents up to 18 A (corresponding to 800 A/cm2) have been obtained. Results allow to get an insight in the physics of operation of the BMFET, to define their theoretical limits of operation, and to understand the reasons for the superior performance of the present device, with respect to the Bipolar Transistor.

Negative resistance induced by avalanche injection in bulk semiconductors

The negative resistance induced by space-charge effects in bulk semiconductor devices subjected to avalanche multiplication has been studied to clarify the physics of this phenomenon and the validity of the assumptions made by other authors. On the basis of the numerical results, an analytical model is proposed, using the regional approximation to evaluate the field along the device and the J-V characteristic. Both the numerical and the analytical results show the role played by the injection of electrons from the cathode and the velocity saturation for the onset of negative resistance, as well as the role of hole injection from the multiplication region near the anode into the bulk for the subsequent voltage lowering. Experimental results are in good agreement with the analytical model in a wide range of device parameters.

Measurement of the effective recombination velocity of semiconductor high-low transitions

A new method for the measurement of the effective recombination velocity (ERV) of high-low transitions is proposed. The method is based upon a test structure that is easily incorporated in the standard process of bipolar devices. The ERV is directly obtained out of simple dc measurements without any critical parameter involved. The ERV can be measured over a wide range of injection levels and its two main components, namely the one due to the high-doped layer and the one due to the retarding region of the transition, can be easily separated from each other.

All-optical multiwavelength technique for the simultaneous measurement of bulk recombination lifetimes and front/rear surface recombination velocity in single crystal silicon samples

In this article, a contactless, all-optical, nondestructive method for separating the minority carrier recombination lifetime and surface recombination velocities in silicon samples at a low injection level is presented. The technique can be described as a pump–probe method in which the excess carrier density is probed by analyzing the free carrier absorption transient following laser pulse excitation that have several wavelengths. An attractive characteristic of the proposed technique is its capability to measure different values of surface recombination velocity on front and back surfaces of the silicon sample. The theoretical foundation of the method is also analyzed. Moreover, numerical simulations which validate the proposed methodology and preliminary experimental results that prove the applicability of scheme are presented.

Comparative analysis of power bipolar devices

A comparison between bipolar Darlington, insulated gate bipolar transistor (IGBT), bipolar mode field effect transistor (BMFET), and power MOS devices is presented based on an experimental investigation performed on devices with similar geometrical characteristics and blocking voltage capabilities. The main device characteristics (conduction characteristics, switching performances, power dissipation, power ratings, etc.) are presented and compared in order to obtain comprehensive guidelines for finding their fields of application. It is shown that, for higher frequency switching application, MOS devices are the most suitable, but they are very expensive in terms of silicon area used. For frequencies less than 20 kHZ, BMFETs have better performance than IGBTs in terms of power losses. On the other hand, the IGBT is a voltage-controlled device and thus has fewer problems with its driving circuit.<<ETX>>

The turnoff transient of the bipolar-mode field-effect transistor

A model of the turnoff transient of the field-effect transistor, operated in the bipolar mode (BMFET), is developed. It is shown that the transient consists of two parts pertaining to the two-carrier and to the one-carrier operations of the device, respectively, the former being much slower than the latter. The model allows the prediction of the switching transient from the basic device parameters; thus, it allows an understanding of the underlying physics of BMFET operation and why the BMFET is faster than other bipolar devices. The mode has also been found to be in good quantitative agreement with experiments, and thus it is a useful tool for the design of the BMFET. >

A two-dimensional analytical model of homojunction GaAs BMFET structures

Abstract The first analytical model of a GaAs-based Bipolar Mode FET (BMFET) device is presented. As a result of a reduced epilayer thickness, the bipolar operation of this class of devices is strongly affected by the transverse path of the drain current underneath the gate, which causes the gate region to be partly debiased. In this article a gate crowding model valid for such a device topology is proposed and then applied to develop an analytical model of the device. Comparison with experimental and numerical results shows clearly that the gate crowding causes a focusing of the drain current in the channel, which, in turn, leads the active area to depend strongly on bias conditions. The results demonstrate the potentiality of this model for an accurate prediction for influence of the geometrical and physical parameters on device performance.

Transverse probe optical lifetime measurement as a tool for in-line characterization of the fabrication process of a silicon solar cell

Abstract In this paper an all-optical measurement procedure for the characterization of minority carrier recombination lifetime and surface recombination velocity is presented as a reliable tool to monitor the fabrication process of a standard crystalline silicon solar cell. In the methodology presented here, there are no stringent requirements concerning the state of wafer surface. The IMEC (Interuniversity Microelectronics Centre, Leuven, Belgium) fabrication process is taken as an example of the capability of this method to monitor the whole process from the silicon wafer to the finished cell. It is shown that the cell process does not degrade the bulk recombination lifetime and that the effect of the external surfaces is effectively screened.

Analysis of stress in power bipolar devices during inductive turn-off

The turnoff transients under inductive load of bipolar junction transistors (BJTs) and bipolar-mode field effect transistors (BMFETs) have been calculated, with the aim of investigating the factors which limit the reverse bias safe operating areas of these devices. Results of 2D simulations which include impact ionization in a self-consistent way show that different device structures exhibit different voltage limitations at high currents, and that, for the same maximum voltage, large differences in the power density distribution can account for the difference in ruggedness which is observed experimentally. The inclusion of a buffer layer in the BJT improves its turnoff performance, provided that this layer is sufficiently thick and doped. In BMFETs the sustaining voltage locus is vertical, and there is no sensitive power concentration at the junction epilayer-substrate, even if no buffer layer is included.<<ETX>>