P. van Gerwen

Microprocessor Implementation of High-Speed Data Modems

This paper describes the application of a commercially available microprocessor (Intel 3000 or Signetics 3000) to a flexible data transmitter and data receiver for high-speed data modems. For the transmitter a quadrature modulation scheme is chosen; the receiver is based on phase-shift compensation techniques and coherent demodulation with an externally derived digital carrier. For the realization with the given microprocessor it has been necessary to adapt the way of executing the various operations (especially the multiplications for the digital filtering) to the available computational capabilities. The resulting microprocessor implementations are also suitable for application in the current medium-speed synchronous data transmission systems.

A New Type of Digital Filter for Data Transmission

A digital filter is introduced consisting of a transversal part and a simple recursive network. The coefficients of the transversal part are equal to integer powers of two or zero; thus complicated multipliers are avoided and instead a simple routing circuit is used. Use of several types of the recursive network makes the filter applicable in different frequency ranges. The coefficients of the transversal part can be interpreted as differences of successive values of the impulse response of the filter. It is shown that this difference routing digital filter (DRDF) is especially suited for application in data transmission.

Design Considerations for a 144 kbit/s Digital Transmission Unit for the Local Telephone Network

In this paper a digital transmission unit for the forthcoming integrated services digital network (ISDN) is considered. Basic elements of such a unit are an adaptive echo canceller (EC) and an adaptive decision feedback equalizer (DFE). Each of these filters can be realized by a transversal filter structure or by a lookup table structure. An analysis and comparison of the behavior of these two structures is given, The combination of an EC and a DFE can also be realized by a single lookup table. It is shown that irrespective of the particular realization three different convergence phases can be distinguished, and that the overall convergence time is considerably longer then would be expected from the usual simple theory that ignores error propagation in the DFE. Two variants of a hardware realization of such a digital transmission unit are presented. They provide 144 kbit/s full-duplex transmission on the symmetrical cables of the existing local telephone network. A small transmission bandwidth is obtained by applying NRZ signaling. In the first circuit the EC and DFE are implemented by individual lookup tables, while in the second a combined table is used. Both circuits are to a large extent, implemented digitally. Due to the relatively low sampling frequency and the acceptably low power consumption they are very well suited for large scale integration with present day technology.

Design of Smearing Filters for Data Transmission Systems

In this paper, we introduce a new approach to design smearing and desmearing filters for data transmission systems to suppress pulse-like disturbances inserted in the communication channel. Our method is based on time domain considerations. It consists of the optimization of two merit factors defined for the impulse response functions of the filters. The first one is a measure of the smearing efficiency, and the second one is a measure of the amount of intersymbol interference caused by the insertion of the two filters in the transmission system. Our method will be applied to smearing and desmearing filters for baseband signals as well as for passband signals. In particular, we show that our method leads to filters having a better smearing efficiency and a simpler implementation than the filters obtained by the classical frequency domain approach.

Data Modems with Integrated Digital Filters and Modulators

The application of a binary transversal filter as transmitting filter and a digital circuit as modulator makes it possible to construct data transmitters consisting only of transistors and resistors. The modulation distortion, caused by the keying of a low-frequency square-wave carrier, can be compensated by a modification of the transfer function of the transmitting filter, provided the carder frequency is chosen to be a multiple of half the bit rate. This principle makes it possible to realize the whole data transmitter in one single integrated circuit. The binary transversal filter, provided with an analog-to-digital converter, can also be used to construct the data receiver for the greater part with digital circuitry.

Architecture and programming of two generations of video signal processors

Abstract Programmable video signal processor ICs (VSPs) and dedicated programming tools have been developed for the real-time processing of digital video signals. A large number of applications have been developed with boards containing several of these processors. Currently two implementations of the general architecture exist: VSP1 and VSP2. A single VSP chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained communication between all elements in a single cycle. The programming of these processors is carried out with signal flow graphs. These signal flow graphs can conveniently express multi-rate algorithms. These algorithms are then mapped onto a network of processors. Mapping is decomposed into delay management, partitioning and scheduling. The solution strategies for the partitioning problem and the scheduling problem are illustrated. Applications with these processors have been made for a number of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and several image improvement algorithms in medical applications. Results of the mapping are presented for a number of algorithms in the field of TV processing.

Novel methods for automatic phase correction of NMR spectra

Abstract A new and simple algorithm for performing fully automatic phase correction of ( in vivo ) NMR spectra with zero-, first-, and even higher-order phase distortions is presented. The method employs the measured phases at the peak positions of spectral lines to calculate the phase distortion. Additionally, two other new methods are discussed. In one method a crude model of the measured spectrum is estimated and deliberately phase-distorted. The phase curve of the spectral model outside the region where the spectral lines are positioned is compared with the phase curve of the measured spectrum over the same regions to iteratively determine the phase distortion. The last method extrapolates the measured time signal to the t = 0 time point. The criterion by which to decide when the applied time shift is correct is derived from the phase curve over the outer regions of the spectrum obtained from this extrapolated time signal. This should be +π/2 at the low-frequency side of the spectral lines and −π/2 at the high-frequency side. The phase distortion is then calculated from the time shift. The feasibility of these new techniques for correcting spectra with low signal-to-noise ratio, overlapping lines, and broad baseline distortions is demonstrated.

Scheduling in programmable video signal processors

The authors discuss the problem of mapping algorithms for real-time processing of digital video signals onto a fixed configuration of identical programmable video signal processors. Due to the periodic nature of the algorithms and the small periods that are involved, successive executions of the algorithm have to be interleaved in time. The resulting scheduling problem is mathematically modeled and examined. The authors present a novel solution approach that is based on a divide-and-conquer strategy using phase assignment as the central part. This approach has been implemented and it gives good results for industrially significant video applications. Specifically, the proposed approach has been implemented in only 1300 lines of C and has been applied to a number of problem instances, whose signal flow graphs originate from industrially relevant algorithms, including contour enhancement and progressive scan, noise reduction, 4:3 to 16:9 screen format conversion, and a very elaborate progressive scan algorithm.<<ETX>>

Architecture and programming of a VLIW style programmable video signal processor

The architecture and programming aspects of a programmable video signal processor are discussed. The processor is an integrated circuit that has a modular architecture with a number of programmable, pipelined processing elements. Networks of these processors can be programmed conveniently with the aid of dedicated programming tools. In this paper the emphasis is on the scheduling of video algorithms and the micro code generation for a network of video signal processors. Due to the periodic nature of the video algorithms and the small periods that are involved, successive executions of the video algorithm have to be interleaved in time. We present a novel solution approach to the scheduling problem using phase assignment as the central part. Results of this approach are presented for industrially significant video applications.

Digital Generation of Linearly Modulated Data Waveforms

A frequency domain analysis of the digital generation of linearly modulated data waveforms is presented. It is shown that for any rational relation of line carrier frequency and digit frequency, digital data transmitters can be designed economically and adapted to large scale integration (LSI) techniques. Special attention is given to the elimination of digital multipliers throughout the system. The results are illustrated with an example of an all-digital vestigialsideband (VSB) transmitter, with a specially shaped output spectrum which facilitates carrier and clock recovery in the receiver.