Harry J. M. Veendrick

High speed current-mode signaling circuits for on-chip interconnects

As the technology scales, the global wire delay becomes a major bottleneck in realizing high performance SOCs. Apart from the technological efforts being made to overcome this problem, it is necessary to develop new circuit design techniques. This paper presents three current-mode circuits for high-speed signal propagation across long on-chip busses. Theoretical analysis has shown that a factor of three can be gained in propagation delay when current-mode (CM) signaling is used in comparison to voltage-mode (VM). In this paper, we show that the delay is reduced by more than a factor of 2 in current mode signaling by using the circuit techniques we propose in comparison to voltage-mode signaling in 0.13 /spl mu/m CMOS technology. This is without any significant power penalty. Further gains in speed are achieved at very high power consumption. The power dissipation on on-chip busses is a strong function of bus layout and data rate. We identified data rates for which the proposed current mode signaling circuits become more power efficient compared to voltage mode signaling circuits.

An efficient and flexible architecture for high-density gate arrays

The properties and performance of high-density gate arrays (HDGAs) are largely determined by the structure on which logic and memory functions are mapped. An architecture for an effective implementation of these functions is presented. All architecture in which each basic cell provides three nMOS and three pMOS transistors is given. Both nMOS and pMOS transistors share a common gate. The advantages of such an architecture can be fully exploited in memory and logic array structures like ROM, RAM, and PLA. Triple-metal BiCMOS processes are at present used to implement HDGAs. Replacing the expensive third metal layer with a TiSi/sub 2/ layer increases the silicon cost and processing time by no more than 5%. These straps are used to bridge only short distances, such as those within logic cells. They are also used for connecting transistors in parallel for increased driving capability. To show the benefits of the common-gate architecture, a 10*10-b fully pipelined multiplier was designed in custom standard cells using commercially available place-and-route software and then in an HDGA architecture.<<ETX>>

Monitors for a signal integrity measurement system

On-chip monitors are an essential part of a signal integrity measurement system. Temperature, voltage and technology monitors need to comply with various boundary conditions, such as lay-out style, available power supply and limited data communication. This paper reports 90 nm and 65 nm monitors

A Digital Field Memory for Television Receivers

In this paper a description and a specification are presented of a 308 kbit digital field memory chip. This device, which is manufactured in a 2 um NMOS process and operates up to 40 MHz, has been designed especially for video applications. Aspects of the design are highlighted with respect to the application in television receivers.

Architecture and programming of two generations of video signal processors

Abstract Programmable video signal processor ICs (VSPs) and dedicated programming tools have been developed for the real-time processing of digital video signals. A large number of applications have been developed with boards containing several of these processors. Currently two implementations of the general architecture exist: VSP1 and VSP2. A single VSP chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained communication between all elements in a single cycle. The programming of these processors is carried out with signal flow graphs. These signal flow graphs can conveniently express multi-rate algorithms. These algorithms are then mapped onto a network of processors. Mapping is decomposed into delay management, partitioning and scheduling. The solution strategies for the partitioning problem and the scheduling problem are illustrated. Applications with these processors have been made for a number of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and several image improvement algorithms in medical applications. Results of the mapping are presented for a number of algorithms in the field of TV processing.

Architecture and Programming of Parallel Video Signal Processors

Publisher Summary The chapter the architecture of two generations of VSPs developed, illustrates the concepts and implementation of the dedicated programming tools, and describes some applications and results associated with them. Programmable video signal processor ICs (VSPs) have been developed for the real-time processing of digital video signals. These processors are supported by dedicated programming tools. A large number of applications have been developed with boards containing several of these processors. The implementation of digital video processing requires a high computing power and a high communication bandwidth because the sampling rates for video signals are in the order of a few to several tens of MHz. Video signal processing can be done with a limited resolution in the number of bits. Currently, two implementations of the general architecture exist: VSP1 and VSP2. A single chip contains several arithmetic and logic elements (ALEs) and memory elements. A complete switch matrix implements the unconstrained communication between all elements in a single cycle. The programming of these processors is done with signal flow graphs (SFGs). These SFGs can conveniently express multi-rate algorithms. These algorithms are mapped onto a network of processors. Applications with these processors have been made for a number of industrially relevant video algorithms, including the complete processing of next generation fully digital studio TV cameras and several image improvement algorithms in medical applications.

Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity

As the technology scales, on-chip interconnects are becoming more and more narrow while their height is not scaling linearly with their width. This leads to an increase in coupling capacitance with neighbouring wires, resulting in higher crosstalk. It also leads to poor performance due to a sluggish RC response at the receiving end of the wire, which may even result in failure in (very) noisy environments. We propose an adaptive threshold scheme in which the receiver switching thresholds are adjusted according to the detected noise in the bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit technique presented in this paper therefore automatically compensates for the process variations. This technique offers a 29% decrease of the propagation delay for a 10 mm long bus in Metal 2 in a 0.13 /spl mu/m CMOS technology in low noise conditions. The total range of control spans 75% of the bus delay.

Encoded-Low Swing Technique for Ultra Low Power Interconnect

We present a novel encoded-low swing technique for ultra low power interconnect. Using this technique and an efficient circuit implementation, we achieve an average of 45.7% improvement in the power-delay product over the schemes utilizing low swing techniques alone, for random bit streams. Also, we obtain an average of 75.8% improvement over the schemes using low power bus encoding alone. We present extensive simulation results, including the driver and receiver circuitry, over a range of capacitive loads, for a general test interconnect circuit and also for a FPGA test interconnect circuit. Analysis of the results prove that as the capacitive load over the interconnect increases, the power-delay product for the proposed technique outperforms the techniques based on either low swing or bus encoding. We also present the signal to noise ratio (SNR) analysis using this technique for a CMOS 0.13μm process and prove that there is a 8.8% improvement in the worst case SNR compared to low swing techniques. This is a consequence of the reduction in the signal switching over the interconnect which leads to lower power supply noise.

Isodelay output driver design using step-wise charging for low power

As the technology is scaling, the on-chip supply voltage is also reducing. However, off-chip communication voltage has failed to keep-up with this trend. The main reason for this is that the ICs in a system are designed by various design houses and in different technologies which require standardized communication interfaces. We present an output driver using energy recycling to communicate with another chip operating at a different/higher voltage through a standardized interface. Charge recycling is performed without any performance penalty. Various circuits, designed for implementing the control circuitry for achieving the charge recovery using step-wise charging, are discussed. The simulation results show that step-wise charging technique is very useful for output drivers driving large loads in the range of 10pF to 30pF. The power savings range from 22% to 35% without much degradation in performance. In fact, performance is improved for most of the cases depending upon the size of the recycling switch used. Furthermore, re-using the charge-recovery current in a DC-DC converter is possible, if certain conditions, as discussed in the paper, are met.

A 40MHz 308Kb CCD video memory

This report will describe a 34.8mm2serial digital field store chip dissipating 350mW and fabricated in a 2μm NMOS modified with one extra mask. Programmable I/O control and 20ms refresh time provide application flexibility.