P. Van Halen

Current-mode amplifier/integrator for a field-programmable analog array

An electronically-programmable analog circuit (EPAC), based on the switched-capacitor (SC) technique, is an analog counterpart of digital FPGAs. The full speed potential of analog circuits, however, can be utilized only by continuous-time (CT) field-programmable analog arrays (FPAAs). In this paper an example of an FPAA structure with local interconnections is shown. Each cell derives a weighted sum of selected signals from four nearest neighbors, and optionally performs integration (ideal or lossy) to produce its own output signal.

A new semiconductor junction diode space charge layer capacitance model

A new expression for the semiconductor junction diode space-charge capacitance has been derived. This new equation preserves the traditional meaning of zero-voltage capacitance and built-in potential and, without introducing any new fitting parameters of its own, eliminates the fitting parameter FC currently used in SPICE. In a single expression, the new model provides an accurate model for the junction capacitance for all reverse bias voltages and for forward bias up to the built-in voltage. Both the capacitance expression and its derivatives are continuous finite values of the diode capacitance for all junction voltages. A charge expression for this new model is also presented, and it is shown that with this expression charge conservation is preserved in circuit simulators.<<ETX>>A new expression for the semiconductor junction diode space-charge capacitance has been derived. This new equation preserves the traditional meaning of zero-voltage capacitance and built-in potential and, without introducing any new fitting parameters of its own, eliminates the fitting parameter FC currently used in SPICE. In a single expression, the new model provides an accurate model for the junction capacitance for all reverse bias voltages and for forward bias up to the built-in voltage. Both the capacitance expression and its derivatives are continuous finite values of the diode capacitance for all junction voltages. A charge expression for this new model is also presented, and it is shown that with this expression charge conservation is preserved in circuit simulators. >

Self-consistent parameter extraction for simulation models

An approach to deriving model parameters in which unique extraction algorithms are developed for each model form is described. Only after consistent extraction routines are developed for the model within a circuit simulator are then applied to the physical device. This provides an exact operational definition for each model parameter. Subsequent optimization, often considered unavoidable, can thus be reduced or eliminated. This approach is the basis of a SPICE model characterization system based on the Tekspice circuit simulator. Bipolar device measurement and Gummel-Poon extraction algorithms created with this system are demonstrated.<<ETX>>

Design of a 2.7 GHz linear OTA in bipolar transistor-array technology with lateral PNPS

The design of a tunable high-frequency fully integrated bipolar operational transconductance amplifier (OTA) is presented. Techniques resulting in tunability and broadbanding are discussed, as well as unavoidable trade-offs resulting from the lack of a vertical positive-negative-positive (PNP) device. Using an 8-GHz bipolar transistor array process, the OTA had a -3-dB frequency response of more than 2.7 GHz and a maximum linear input range of +or-2.5 V, and it dissipated 28 mW for a power supply of +or-5 V. Two applications of the OTA in OTA-C filter design are presented.<<ETX>>

60 MHz common-mode self-tuned continuous-time filter for mass-storage applications

Mass-storage channels with bit rates in excess of 100 Mb/s require continuous-time filters with cutoff-frequencies above 40 MHz. At those frequencies, even for Q-factors as low as 2, phase errors may justify the use of a separate Q-control if the required linear phase response of the filter is to be guaranteed. Because of the tight power budget, bipolar designs may have an advantage over CMOS and BiCMOS designs, combining high speed, low power, and low noise levels. The filter, built using a 9 GHz bipolar process, is furnished with both frequency- and Q-tuning schemes. It operates up to 60 MHz, and so can be applied in higher-order channel filters working in the 25-40 MHz range. The filter is truly self-tuned, i.e., it can be tuned while processing signals by simultaneously applying to the input a differential-mode (DM) signal and a common-mode (CM) reference.

A new SPICE-compatible model and related self-consistent parameter extraction for the dual-gate JFET

A model for the dual-gate JFET is presented. The major improvement over previous models is the capability to bias the top gate and bottom gate independently. This is accomplished through the use of a controlled voltage source with two controlling inputs and with its output driving the gate terminal of the JFET. Since the model can be represented as a subcircuit, it is compatible with SPICE and SPICWE-derived circuit simulators. Self-consistent parameter extraction routines based on an exact operational definition of each model parameter are discussed. Unique extraction algorithms are developed for each model form. Only after consistent extraction routines have been developed for the model within a circuit simulator are they applied to the physical device. This provides an exact operational definition for each model parameter. Accurate determination of the model parameters without optimization has been proven possible, and excellent agreement between physical devices and simulation results is demonstrated.<<ETX>>

Characterization of junction capacitance parameters for Gaussian/constant doping profiles

A new model for the junction capacitance parameters for junctions that can be described by a Gaussian/constant doping profile is presented. The model relies on accurate approximations for the error function and its integral. On the basis of these approximations, routines which accurately predict the built-in potential of the junction and the zero-bias junction capacitances for a wide range of junction parameters have been constructed. Values of the built-in potential, zero-bias capacitance, and capacitance versus voltage characteristics for typical junction parameters are shown. >A new model for the junction capacitance parameters for junctions that can be described by a Gaussian/constant doping profile is presented. The model relies on accurate approximations for the error function and its integral. On the basis of these approximations, routines which accurately predict the built-in potential of the junction and the zero-bias junction capacitances for a wide range of junction parameters have been constructed. Values of the built-in potential, zero-bias capacitance, and capacitance versus voltage characteristics for typical junction parameters are shown.<<ETX>>

A physical charge-based model for the space charge region of abrupt and linear semiconductor junctions

A new, physically justified, charge-based expression for the semiconductor space charge region capacitance is derived. This equation preserves the traditional meaning of zero-voltage capacitance, built-in potential and junction grading coefficient and, without introducing any new fitting parameters of its own, eliminates the fitting parameter FC currently used in SPICE. This new model eliminates the singularity found in the depletion approximation model, is applicable for any applied voltage, and being charge-based does not suffer from charge-conservation problems reported for capacitance based formulations. In this paper, the new model is formulated and compared with charge/capacitance results extracted from PISCES. >

A new model for the p-n junction space charge region capacitance

Depletion-approximation-based junction capacitance versus voltage characteristics are adequate for reverse bias but, contrary to experiments and computer simulations, predict an infinite capacitance when the applied voltage equals the built-in potential. A new, physically justified model for the semiconductor space charge region capacitance is derived. This new model takes only three input parameters, i.e., the zero bias capacitance, the built-in potential and the junction grading coefficient, thus eliminating the fitting parameter FC currently used in SPICE (Simulation Program with IC Emphasis). This new model eliminates the singularity found in the depletion approximation model and is applicable for any applied voltage. This new model is compared with capacitance results extracted from the PSPICES device simulator and with earlier capacitance model formulations.<<ETX>>

Low-voltage Gilbert current-gain cell

A modified Gilbert current gain cell works with a single supply voltage as low as 1.5 V (2V/sub BE/) and reduced power consumption. The circuit inherits most features of the original cell, including the ability to be cascaded without increasing the supply voltage. No special technological features are required to implement the circuit. The design has been verified experimentally using CA 3046 and CA 3096 transistor arrays.