Pablo A. Ferreyra

Digital lock in amplifier: study, design and development with a digital signal processor

Abstract In this work, the study, design and development of a Digital Lock In Amplifier (DLIA) with a Digital Signal Processor (DSP) DSP32C from AT&T is presented. To synchronize the DLIA oscillator with external signal, a Discrete Phase Locked Loop (DPLL) is added to the systems. A theoretical introduction of both systems is also presented. The algorithm of the DPLL presented is valid only for constant uniform sampling frequency.

Injecting bit flip faults by means of a purely software approach: a case studied

Bit flips provoked by radiation are a main concern for space applications. A fault injection experiment performed using a software simulator is described in this paper. Obtained results allow us to predict a low sensitivity to soft errors for the studied application, putting in evidence critical memory elements.

Injecting single event upsets in a digital signal processor by means of direct memory access requests: a new method for generating bit flips

In this paper a novel approach for injecting Single Event Upsets, (SEU), by means of direct memory access, (DMA), mechanisms is presented. The system consists in a PC based control unit that generates DMA requests randomly in time to a board containing the processor under test, and a test unit. Experimentation performed on a digital signal processor intended to be used in a satellite project illustrates the potentialities of the proposed approach.

Failure and Coverage Factors Based Markoff Models: A New Approach for Improving the Dependability Estimation in Complex Fault Tolerant Systems Exposed to SEUs

Dependability estimation of a fault tolerant computer system (FTCS) perturbed by single event upsets (SEUs) requires obtaining first the probability distribution functions for the time to recovery (TTR) and the time to failure (TTF) random variables. The application cross section (sigmaAP) approach does not give directly all the required information. This problem can be solved by means of the construction of suitable Markoff models. In this paper, a new method for constructing such models based on the systems failure and coverage factors is presented. Analytical dependability estimation is consistent with fault injection experiments performed in a fault tolerant operating system developed for a complex, real time data processing system.

Assessing DTN architecture reliability for distributed satellite constellations: Preliminary results from a case study

Networked small satellites constellations can yield, in general, not only higher revisit rates but new mission opportunities with important cost and risk saving by means of successive small launches and distributed functionalities such as payload, storage, processing, or data downlink. Nevertheless, as this networks operates in challenged environments, they usually face resources constraints; moreover, orbital dynamics might impose sporadic channel availability. As a result, these intermittent inter-satellite communications challenges existing networking protocols as they assume persistent connectivity. To this end, Delay Tolerant Networking (DTN) has emerged as an automated store-carry-and-forward communication architecture capable to cope with contact disruption. In order to assess DTN reliability, we generalize the communications disruptions to also include transient and permanent component faults so as to demonstrate that DTN architecture result inherently fault tolerant as failures no longer implies a service outage but an overall system capacity degradation. To this end, we developed a network model encompassing DTN communication protocols, routing algorithms, and satellite failure models to measure the system capacity degradation under specific constellation topologies.

OpenCL Overview, Implementation, and Performance Comparison

High performance parallel computing was something exclusive for expensive specialized hardware some years ago. But now we can find powerful parallel processors in many home graphics card whose interface has been recently opened by many manufacturers for general purpose computing. OpenCL, created by the world most important processors manufacturers, went a little further, aiming for a platform and manufacturer independent parallel language. However, understanding this new processing paradigm is challenging and critical for future computation demanding applications. The first approach of this document is to provide a deep technical background of OpenCL architecture. Second, we propose an implementation of a matrix product calculation OpenCL kernel directly implemented in C++ without wrappers so as to describe in detail the OpenCL programming flow. Thirdly, different platforms and algebraic scenarios are created for this program concluding that the improvement of calculation performance can reach up to 3 orders of magnitude over the same algorithm in plain C++.

Internetworking approaches towards along-track segmented satellite architectures

The Argentinian Space Agency (CONAE) has been pursuing the development of segmented satellite architectures as a novel strategy to reduce the cost and improve responsiveness of space access. Among the key enablers for these architectures, wireless communication is likely to be the most critical as it requires to operate on a highly dynamic, sparse and extreme environments. In this work, we analyze and derive the main specifications that a communication system for segmented architectures (CSSA) must support. In particular, we provide an abstract model to predict the access time to segmented systems to later propose a layered arrangement of the main specifications for the CSSA. Finally, we analyze by simulation a particular CSSA configuration in a simple yet representative scenario with an along-track flight formation.

Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs

Fault injection is a well-known technique to evaluate the susceptibility of integrated circuits to the effects of radiation. In this work, an existing emulation-based methodology is extended, updated and improved under the name of NETFI-2. Preliminary results show that NETFI-2 provides accurate measurements while improving the execution time of the experiment by more than 300% compared with other simulation-based campaigns.

Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications

This work presents a Fault Tolerant FPGA based Active Antenna system intended to be used in the space environment. The proposed design can control the electromagnetic radiation pattern emitted by an antenna array in real time with high reliability levels. The FPGA is a Commercial of the Shelf (COTS) device based on the Anti fuse technology. The design is optimized to reduce the area overhead allowing the control of multiple antennas by means of a single FPGA. The Fault Tolerance and high reliability achieved with the design is shown by means of a new test methodology.