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A Nanowatt Smart Temperature Sensor for Dynamic Thermal Management

The amazing integration densities achieved by current submicron technologies pay the price of increasing static power dissipation with the corresponding rise in heat density. Dynamic thermal management (DTM) techniques provide thermal-efficient solutions to balance or equally distribute possible on-chip hot spots. Accurate sensing of on-chip temperature is required by optimally allocating smart temperature sensors in the silicon. In this paper, we introduce an ultra low-power (1.05 - 65.5 nW at 5 samples/s) tiny (10250 mum2) CMOS smart temperature sensor based on the thermal dependency of the leakage current. The proposed sensor outperforms all previous works, as far as area and power consumption are concerned (more than 85% reduction in both cases), while still meeting the accuracy constraints imposed by target application domains. Furthermore, a specific interface based on the use of a logarithmic counter has been implemented to digitalize the temperature sensing. These facts, in conjunction with the full compatibility of the sensor with standard CMOS processes, allow the easy integration of many of these tiny sensors in any VLSI layout, making them specially suitable for modern DTM implementations.

Leakage-based On-Chip Thermal Sensor for CMOS Technology

Thermal characterization of ICs and on-chip temperature monitoring have become key tasks in electronic engineering. In this paper, we present the design of an on-chip CMOS temperature sensor based on the temperature dependent characteristics of the subthreshold current. The proposed sensor achieves high accuracy sensing (0.56 degC maximum error), wide temperature range (25-90 degC), and extremely low area (0.010 mm2) and power overhead (18 muW). Our approach improves previous works on on-chip temperature sensors and is highly suitable for portable applications where temperature monitoring achieves great importance.

New Schemes in Clustered VLIW Processors Applied to Turbo Decoding

State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for innovative solutions. In recent years the area of application specific processors has attracted the attention of the research community and important advances have been made possible. This work introduces an ASIP architecture for SISO Turbo decoding based on a dual-clustered VLIW processor. The machine deals with instructions of up to 21 operands in an innovative way, the fetching and asserting of data is serialized and the addressing is automatized and transparent for the programmer. An optimized architecture is achieved, flexible enough to comply with leading edge standards and adaptable to demanding hardware constraints.

Light-Weight On-Chip Monitoring Network for Dynamic Adaptation and Calibration

Current nanometer technologies suffer within-die parameter uncertainties, varying workload conditions, aging, and temperature effects that cause a serious reduction on yield and performance. In this scenario, monitoring, calibration, and dynamic adaptation become essential, demanding systems with a collection of multi purpose monitors and exposing the need for light-weight monitoring networks. This paper presents a new monitoring network paradigm able to perform an early prioritization of the information. This is achieved by the introduction of a new hierarchy level, the threshing level. Targeting it, we propose a time-domain signaling scheme over a single-wire that minimizes the network switching activity as well as the routing requirements. To validate our approach, we make a thorough analysis of the architectural trade-offs and expose two complete monitoring systems that suppose an area improvement of 40% and a power reduction of three orders of magnitude compared to previous works.

Building Memristor Applications: From Device Model to Circuit Design

Since the memristor was first built in 2008 at HP Labs, no end of devices and models have been presented. Also, new applications appear frequently. However, the integration of the device at the circuit level is not straightforward, because available models are still immature and/or suppose high computational loads, making their simulation long and cumbersome. This study assists circuit/systems designers in the integration of memristors in their applications, while aiding model developers in the validation of their proposals. We introduce the use of a memristor application framework to support the work of both the model developer and the circuit designer. First, the framework includes a library with the best-known memristor models, being easily extensible with upcoming models. Systematic modifications have been applied to these models to provide better convergence and significant simulations speedups. Second, a quick device simulator allows the study of the response of the models under different scenarios, helping the designer with the stimuli and operation time selection. Third, fine tuning of the device including parameters variations and threshold determination is also supported. Finally, SPICE/Spectre subcircuit generation is provided to ease the integration of the devices in application circuits. The framework provides the designer with total control overconvergence, computational load, and the evolution of system variables, overcoming usual problems in the integration of memristive devices.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensors measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration.

A 0.0016 mm2 0.64 nJ Leakage-Based CMOS Temperature Sensor

This paper presents a CMOS temperature sensor based on the thermal dependencies of the leakage currents targeting the 65 nm node. To compensate for the effect of process fluctuations, the proposed sensor realizes the ratio of two measures of the time it takes a capacitor to discharge through a transistor in the subthreshold regime. Furthermore, a novel charging mechanism for the capacitor is proposed to further increase the robustness against fabrication variability. The sensor, including digitization and interfacing, occupies 0.0016 mm2 and has an energy consumption of 47.7–633 pJ per sample. The resolution of the sensor is 0.28 °C, and the 3σ inaccuracy over the range 40–110 °C is 1.17 °C.

A monitoring infrastructure for FPGA self-awareness and dynamic adaptation

Variabilities associated with CMOS evolution affect the yield and performance of current digital designs. FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues. Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network. This infrastructure, through adequate use of configuration and automation tools, is able to obtain relevant data along the life cycle of an FPGA. This is realised at a very reduced cost, not only in terms of area or other limited resources, but also regarding the design effort required to define and deploy the measuring infrastructure. Our proposal has been validated by measuring inter-die and intra-die variability in different FPGA families.

Ratio-Based Temperature-Sensing Technique Hardened Against Nanometer Process Variations

This letter presents a temperature-sensing technique on the basis of the temperature dependency of MOSFET leakage currents. To mitigate the effects of process variation, the ratio of two different leakage current measurements is calculated. Simulations show that this ratio is robust to process spread. The resulting sensor is quite small-0.0016 mm2 including an analog-to-digital conversion-and very energy efficient, consuming less than 640 pJ/conversion. After a two-point calibration, the accuracy in a range of 40°C-110°C is less than 1.5°C , which makes the technique suitable for thermal management applications.

A Configurable Application Specific Processor for Turbo Decoding

Turbo codes provide an astonishing performance, however their complex decoder structure entails a power and area consuming VLSI implementation. To overcome this problem we present an application specific processor architecture that clearly outperforms previous implementations. In particular, a simpler normalization scheme for the state metrics is used and a higher degree of concurrency is achieved with little hardware overhead thanks to the optimized use of the butterfly pair structure. Moreover, the resulting architecture is characterized by a great flexibility and programmability —Log-MAP and Max-LogMAP algorithms, direct procedure and sliding windows mechanism— accomplishing with several industrial standards such as UMTS and CDMA2000 among others. The architecture has been prototyped in a VirtexII FPGA.