Fernando Garcia-Redondo

Building Memristor Applications: From Device Model to Circuit Design

Since the memristor was first built in 2008 at HP Labs, no end of devices and models have been presented. Also, new applications appear frequently. However, the integration of the device at the circuit level is not straightforward, because available models are still immature and/or suppose high computational loads, making their simulation long and cumbersome. This study assists circuit/systems designers in the integration of memristors in their applications, while aiding model developers in the validation of their proposals. We introduce the use of a memristor application framework to support the work of both the model developer and the circuit designer. First, the framework includes a library with the best-known memristor models, being easily extensible with upcoming models. Systematic modifications have been applied to these models to provide better convergence and significant simulations speedups. Second, a quick device simulator allows the study of the response of the models under different scenarios, helping the designer with the stimuli and operation time selection. Third, fine tuning of the device including parameters variations and threshold determination is also supported. Finally, SPICE/Spectre subcircuit generation is provided to ease the integration of the devices in application circuits. The framework provides the designer with total control overconvergence, computational load, and the evolution of system variables, overcoming usual problems in the integration of memristive devices.

SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds

In this work, we propose a physical memristor/resistive switching device SPICE compact model, that is able to accurately fit both unipolar/bipolar devices settling to its current-voltage relationship. The proposed model is capable of reproducing essential device characteristics such as multilevel storage, temperature dependence, cycle/event handling and even the evolution of variability/parameter degradation with time. The developed compact model has been validated against two physical devices, fitting unipolar and bipolar switching. With no requirement of Verilog-A code, LTSpice, and Spectre simulations reproduce distinctive phenomena such as the preforming state, voltage/cycle dependent random telegraph noise and device degradation.

Reliable design methodology: The combined effect of radiation, variability and temperature

The effects caused by variability, temperature, radiation or aging may compromise the reliability of electronic circuits. Circuits designers must consider their combined effects early during the design cycle, even though it is a time and effort demanding task. In this work we present a methodology and simulation framework for the reliable design of circuits working under realistic conditions such as a wide range of temperatures, radiation and process variations. This proposal provides an alternative method for validating digital and analog circuits. Depending on the analyzed circuit functionality, the user is able to define complex reliability metrics such as signal upsets, delays or frequency deviations to measure the circuit response in affordable simulation time.

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm

New CMOS technologies such as SOI or FinFET are expected to enhance SRAM radiation-induced soft error rates thanks to a reduction on the charge collected as the devices get smaller. In this work we analyze how the radiation hardening capabilities of SRAMs are affected when process variations are considered by simulating cells using a predictive FinFET technology. The results show that even if the average critical charge to which SRAM cells are vulnerable is enhanced by process variations, its widened spread leads to an increase of the soft error rate by more than 40% as the technology node is scaled down to 7nm.

A tool for the automatic analysis of single events effects on electronic circuits

Nowadays integrated circuit reliability is challenged by both variability and working conditions. Environmental radiation has become a major issue when ensuring the circuit correct behavior. The required radiation and later analysis performed to the circuit boards is both fund and time expensive. The lack of tools which support pre-manufacturing radiation hardness analysis hinders circuit designers tasks. This paper describes an extensively customizable simulation tool for the characterization of radiation effects on electronic systems. The proposed tool can produce an in depth analysis of a complete circuit in almost any kind of radiation environment in affordable computation times.

A CAD framework for the characterization and use of memristor models

In the recent years the missing fourth component, the memristor, was successfully synthesized. However, the mathematical complexity and variety of the models behind this component, in addition to the existence of convergence problems in the simulations, make the design of memristor-based applications long and difficult. In this work we present a memristor model characterization framework which supports the automated generation of subcircuit files. The proposed environment allows the designer to choose and parameterize the memristor model that best suits for a given application. The framework carries out characterizing simulations in order to study the possible non-convergence problems, solving the dependence on the simulation conditions and guaranteeing the functionality and performance of the design. Additionally, the occurrence of undesirable effects related to PVT variations is also taken into account. By performing a Monte Carlo or a corner analysis, the designer is aware of the safety margins which assure the correct device operation.

Temperature sensor placement including routing overhead and sampling inaccuracies

Dynamic thermal management techniques require a collection of on-chip thermal sensors that imply a significant area and power overhead. Finding the optimum number of temperature monitors and their location on the chip surface to optimize accuracy is an NP-hard problem. In this work we improve the modeling of the problem by including area, power and networking constraints along with the consideration of three inaccuracy terms: spatial errors, sampling rate errors and monitor-inherent errors. The problem is solved by the simulated annealing algorithm. We apply the algorithm to a test case employing three different types of monitors to highlight the importance of the different metrics. Finally we present a case study of the Alpha 21364 processor under two different constraint scenarios.

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges

Resistive switching memories [resistive RAM (RRAM)] are an attractive alternative to nonvolatile storage and nonconventional computing systems, but their behavior strongly depends on the cell features, driver circuit, and working conditions. In particular, the circuit temperature and writing voltage schemes become critical issues, determining resistive switching memories performance. These dependencies usually force a design time tradeoff among reliability, device endurance, and power consumption, thereby imposing nonflexible functioning schemes and limiting the system performance. In this paper, we present a writing architecture that ensures the correct operation no matter the working temperature and allows the dynamic load of application-oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection, and operation speed, showing speedups near

Characterization of analog modules: Reliability analyses of radiation, temperature and variations effects

700\times

A thermal adaptive scheme for reliable write operation on RRAM based architectures

compared with other published drivers.