Carlos Alberto López Barrio

SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems

In this article we describe SORU, a reconfigurable instruction set processor architecture (RISP) specially designed for run-time self-adaptation in environments with tight resource and power restrictions. It allows to accelerate computationally intensive multimedia processing on portable/embedded devices while maintaining a low energy consumption. The experimental results show a mean speedup of 4 with half the energy consumption. The main datapath can be left in a hibernate state during more than 75% of the execution time in our experiments, what leads also to a significant reduction of energy consumption in the I-cache and the main datapath, including the register file.

A CAD framework for the characterization and use of memristor models

In the recent years the missing fourth component, the memristor, was successfully synthesized. However, the mathematical complexity and variety of the models behind this component, in addition to the existence of convergence problems in the simulations, make the design of memristor-based applications long and difficult. In this work we present a memristor model characterization framework which supports the automated generation of subcircuit files. The proposed environment allows the designer to choose and parameterize the memristor model that best suits for a given application. The framework carries out characterizing simulations in order to study the possible non-convergence problems, solving the dependence on the simulation conditions and guaranteeing the functionality and performance of the design. Additionally, the occurrence of undesirable effects related to PVT variations is also taken into account. By performing a Monte Carlo or a corner analysis, the designer is aware of the safety margins which assure the correct device operation.

Implementation tradeoffs of triangle traversal algorithms for graphics processing

Current CPU architectures provide high processing rates in graphical applications because of their specialized graphics pipeline. So far, little attention has been paid in the scientific literature to the analysis and study of different hardware structures that implement specific pipeline stages. In this work we have identified one of the key stages in the graphics pipeline, the triangle traversal procedure, and we have implemented it in a 90 nm standard cell technology, comparing three different algorithms: Bounding-box, Zig-zag and Hilbert curve-based. The experimental results show that important area-latency-frequency-throughput tradeoffs must be taken into account for the implementation of the triangle traversal stages. Furthermore, since power is a main concern in CPUs, we have studied how some triangle characteristics such as the shape, size, position and depth affect the power consumption.

Advanced integration of variability and degradation in RRAM SPICE compact models

Variability and degradation in RRAM devices involve complex physical mechanisms that depend on the device, environment and programming/read operation. The development of solid and accurate compact models, ready to be used in standard circuit simulators, requires the meticulous emulation of this kind of non-ideal effects. In this work we present an advanced approach for the emulation of complex variability and degradation effects in SPICE compacts models. Without requiring compiled components — such as Verilog-A or CMI code — the proposed solution can be adapted to any kind of memristor model providing full support to the emulation of these intricate behaviors. Thorough experiments illustrate the capabilities of the presented approach. There, we make use of a physical SPICE model that emulates behavioral dependence on the device cycling, simulation time and stress levels. After applying the proposed techniques, we obtain an enhanced model properly aware of the devices non-ideal behavior.

Four-injector variability modeling of FinFET predictive technology models

The usual way of modeling variability using threshold voltage shift and drain current amplification is becoming inaccurate as new sources of variability appear in sub-22nm devices. In this work we apply the four-injector approach for variability modeling to the simulation of SRAMs with predictive technology models from 20nm down to 7nm nodes. We show that the SRAMs, designed following ITRS roadmap, present stability metrics higher by at least 20 % compared to a classical variability modeling approach. Speed estimation is also pessimistic, whereas leakage is underestimated if sub-threshold slope and DIBL mismatch and their correlations with threshold voltage are not considered.