Spiridon Nikolaidis

Propagation delay and short-circuit power dissipation modeling of the CMOS inverter

This paper introduces a new, accurate analytical model for the evaluation of the delay and the short-circuit power dissipation of the CMOS inverter. Following a detailed analysis of the inverter operation, accurate expressions for the output response to an input ramp are derived. Based on this analysis improved analytical formulae for the calculation of the propagation delay and short-circuit power dissipation, are produced. Analytical expressions for all inverter operation regions and input waveform slopes are derived, which take into account the influences of the short-circuit current during switching, and the gate-to-drain coupling capacitance. The effective output transition time of the inverter is determined in order to map the real output voltage waveform to a ramp waveform for the model to be applicable in an inverter chain. The final results are in very good agreement with SPICE simulations.

Energy Consumption Estimation in Embedded Systems

This paper presents an energy consumption modeling technique for embedded systems based on a microcontroller. The software tasks that run on the embedded system are profiled, and their characteristics are analyzed. The type of executed assembly instructions, as well as the number of accesses to the memory and the analog-to-digital converter, is the required information for the derivation of the proposed model. An appropriate instrumentation setup has been developed for measuring and modeling the energy consumption in the corresponding digital circuits.

Real-time canny edge detection parallel implementation for FPGAs

Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector is the most implemented edge detection algorithm because of its ability to detect edges even in images that are intensely contaminated by noise. However, this is a time consuming algorithm and therefore its implementations are difficult to reach real time response speeds. Especially nowadays where the demand for high resolution image processing is constantly increasing, the need for fast and efficient edge detector implementations is ever so present. A new parallel Canny edge detector FPGA implementation is proposed in this paper to answer this demand. This design takes advantage of 4-pixel parallel computations to achieve high throughput without increasing the on-chip memory demands. Synthesis and simulation results are presented to prove the designs efficiency and high frames per second rate.

Instruction-level power consumption estimation embedded processors low-power applications

A power consumption measurement framework for embedded processing systems is presented in this work. Given an assembly or machine level program as input to this setup, the energy consumption of the specific program in the specific processing systems may be estimated. The instruction level power models are derived based on the power supply current measurement technique. The instantaneous variations of the power supply current provide the appropriate information for the accurate estimation of the power consumption at different operating situations of the processor (core) and of the overall processing system as well (consumption of peripheral units). The proposed instantaneous current measuring approach, along with the execution of special test programs for analysis of inter-instruction effects provides a clear insight into the power behavior of embedded processing systems.

Measurement of current variations for the estimation of software-related power consumption [embedded processing circuits]

A current measurement configuration for the estimation of the power consumption of processing systems is presented in this work. The problem addressed is to measure the variations of the power supply current of digital circuits (and especially of embedded processing circuits) and to calculate from these measurements the energy consumption variations associated with certain tasks performed by the system software. Accurate monitoring of the instantaneous variations of the power supply current provides the appropriate information for the estimation of the power consumption at different operating situations of the processor (core) and of the overall processing system, as well (consumption of peripheral units). The proposed instantaneous current measuring approach, along with the execution of special test programs for analysis of inter-instruction effects, is expected to provide clear information of the power behavior of single-chip processing systems for low-power applications.

Measurements analysis of the software-related power consumption in microprocessors

In this paper the measurements taken for the development of instruction-level energy models for microprocessors are presented and analyzed. An appropriate measuring environment and a suitable measuring methodology were developed for taking the necessary measurements. The energy of an instruction is defined as a sum of three components. The pure base energy cost, the inter-instruction cost and the effect of the energy sensitive factors (instruction parameters). These components are characterized for each instruction of the ARM7TDMI embedded processor and their values are analyzed. Using the resulted models estimates of the energy consumption of real software kernels with only up to 5% error was determined.

Instruction level energy modeling for pipelined processors

A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.

Modeling CMOS gates driving RC interconnect loads

The problem of estimating the performance of CMOS gates driving RC interconnect loads is addressed in this paper. The widely accepted /spl pi/-model is used for the representation of an interconnect line that is driven by an inverter. The output waveform and the propagation delay of the inverter are analytically calculated taking into account the coupling capacitance between input and output and the effect of the short-circuit current. In addition, short-circuit power dissipation is accurately estimated. Once the voltage waveform at both the beginning and the end of an interconnect line are obtained, a simple method is employed in order to calculate the voltage waveform at each point of the line.

Low-power/low-swing domino CMOS logic

A new low-power domino CMOS logic is introduced. Its power characteristics are based on a low voltage swing technique. The output inverter of the domino gate is modified in order to reduce its output voltage swing. This results in dynamic power dissipation saving up to 36% and improvement in the power-delay product. A technique for creating changeable values of the voltage swing is used achieving various trade-off between power savings and speed. Experimental results clearly show the validity of the proposed technique for low-power operation.

Delay and power estimation for a CMOS inverter driving RC interconnect loads

The resistive-capacitive behavior of long interconnects which are driven by CMOS gates is analyzed in this paper. The analysis is based on the /spl pi/-model of an RC load and is developed for submicron devices. Accurate and analytical expressions for the output voltage waveform, the propagation delay and the short circuit power dissipation are derived by solving the system of differential equations which describe the behavior of the circuit. The effect of the coupling capacitance between input and output and that of short circuit current are also incorporated in the proposed model. The calculated propagation delay and short circuit power dissipation are in very good agreement with SPICE simulations.