Panagiotis Oikonomou

Particle Swarm Optimization Approach for Fuzzy Cognitive Maps Applied to Autism Classification

The task of classification using intelligent methods and learning algorithms is a difficult task leading the research community on finding new classifications techniques to solve it. In this work, a new approach based on particle swarm optimization (PSO) clustering is proposed to perform the fuzzy cognitive map learning for classification performance. Fuzzy cognitive map (FCM) is a simple, but also powerful computational intelligent technique which is used for the adoption of the human knowledge and/or historical data, into a simple mathematical model for system modeling and analysis. The aim of this study is to investigate a new classification algorithm for the autism disorder problem by integrating the Particle Swarm Optimization method (PSO) in FCM learning, thus producing a higher performance classification tool regarding the accuracy of the classification, and overcoming the limitations of FCMs in the pattern analysis area.

Bagged nonlinear hebbian learning algorithm for fuzzy cognitive maps working on classification tasks

Learning of fuzzy cognitive maps (FCMs) is one of the most useful characteristics which have a high impact on modeling and inference capabilities of them. The learning approaches for FCMs are concentrated on learning the connection matrix, based either on expert intervention and/or on the available historical data. Most learning approaches for FCMs are Hebbian-based and evolutionary-based algorithms. A new learning algorithm for FCMs is proposed in this research work, inheriting the main aspects of the bagging approach which is an ensemble based learning approach. The FCM nonlinear Hebbian learning (NHL) algorithm enhanced by the bagging technique is investigated contributing to an approach where the model is trained using NHL algorithm as a base learner classifier. This work is inspired from the neural networks ensembles and it is used to learn the FCM ensembles produced by the NHL exploiting better classification accuracies.

Domocus: Lock free parallel legalization in standard cell placement

In the cell placement problem a circuits cells must be placed within a specified chip area so that they are row aligned and contain no overlaps. The problem is usually tackled in phases, whereby in the first phase a global placer performs an initial spreading of cells with regards to some optimization criterion, most commonly wire length minimization. The output of the first phase might violate alignment and overlap constraints, therefore in a second phase, called legalization, the target is to restore constraint violations while incurring minimal changes compared to global placement. Since legalization may also be a subcomponent of iterative global placers, efficient algorithms both in terms of solution quality and running time are of paramount importance. In this paper we present a framework for lock-free parallelism of legalization scheme. The framework is evaluated using Abacus, an algorithm that is well documented to achieve good solution quality but incurring high running time. We term the resulting legalization algorithm Domocus. Through experiments with commonly used benchmark circuits, we conclude on the scalability and efficiency of Domocus.

The Implementation of a Web Application for Screening Children with Dyslexia

Developmental dyslexia is defined as an unexpected specific and persistent failure to acquire efficient reading skills despite conventional instruction, adequate intelligence and sociocultural opportunity. The main aim of the present research protocol was to construct a web screening battery of tests in order to screen children’s reading, orthographic and cognitive skills. The main hypothesis of the present study was that Greek students that were already diagnosed as dyslexic, shall present significantly lower scores. A total of sixty, right handed children (30 male and 30 female, age range 8–11 years old M = 8.93, SD = 0.83) participated in this study. Reading, cognitive and orthographic skills of children with dyslexia and typically achieving children were examined, using a battery that consisted of seven tasks. Subsequent analysis of variance revealed that the children with dyslexia had statistically significant (p < 0.01) lower mean scores of correct answers and larger latencies in all tasks compared to their average peers that participated at the control group.

Performance Evaluation of Tetris-based Legalization Heuristics

Algorithms for standard cell placement legalization have attracted significant research efforts in the past. A prominent member of this category is the Tetris algorithm which is a simple and particularly fast method for legalizing an initial placement containing overlaps. In the relevant literature sophisticated legalization schemes were proposed using Tetris as a performance yardstick. In order to achieve better performance such schemes usually sacrifice the fast running time of Tetris by a large margin. In this paper we turn our focus on simple Tetris variations that improve performance without seriously compromising running time. Specifically, we present five generic heuristic variations of the initial Tetris algorithm. Through experimental evaluation we conclude on the merits of each approach.

On Green Scheduling for Desktop Grids

Task scheduling is of paramount importance in a desktop grid environment. Earlier works in the area focused on issues such as: meeting task deadlines, minimizing make-span, monitoring and checkpointing for progress, malicious or erroneous peer discovery and fault tolerance using task replication. More recently energy consumption has been studied from the standpoint of judiciously replicating and assigning tasks to the more power efficient peers. In this paper we tackle another aspect of power efficiency with regards to scheduling, namely greenness of the consumed energy. We give a formulation as a multi-objective optimization problem and propose heuristics to solve it. All the heuristics are evaluated via simulation experiments and conclusions on their merits are drawn.

WEVIAN: A Web-based Placement Visualizer / Analyzer

One of the most important stages of a typical ASIC (Application-specific integrated circuit) design flow, is physical design. The most prominent step of the aforementioned stage is placement. Major design challenges are regulated while traversing this stage in order to accommodate the final sign-off. Various aspects of the design might be modified during this step, and the primary manner to keep track of these modifications is usually through detailed text reports, concerning universal metrics like density and wire-length, and generic static visualizations, due to the timing overhead it introduces to the overall procedure. However, a detailed and interactive depiction of the final result might provide insights concerning the quality of the final solution and the effectiveness of the applied algorithms. In this paper we present WEVIAN, a web-based placement visualizer/analyzer that enhances the design procedure by adding interactivity and offloading part of the workload to a third-party server.

SCIZER: A scalable placement visualizer/analyzer

The major design challenges of ASIC design, like power dissipation, timing, voltage-drop, interconnect and reliability are tackled during the Physical Design phase of any flow. The placement procedure can significantly modify parts of the design and consequently metrics relevant to the aforementioned challenges. Text reports cannot always generate useful insight based solely on these metrics. Design visualization can be of utmost importance in deciding if the placement strategy followed is leading to fruition. In this paper we present a placement visualizer/analyzer that helps capture the most critical aspects of a placed design and empowers the user to draw safer conclusions concerning the quality of the final result.

Enhanced Tetris Legalization

Legalization and detailed placement methods for standard cell designs, are two of the most notable topics in current VLSI research. Being the final steps in a classic placement procedure they must be efficient in terms of the delay overhead they introduce to the overall design flow and the quality of the final solution. In this paper we present a combined solution of the aforementioned steps, based on Tetris a particular simple and fast legalization algorithm, that produces considerable results taking into account the tradeoff between total wirelength, total cell displacement and runtime.

Heuristics for Iterative Detailed Standard Cell Placement

In cell placement a number of cells with rectangular shapes, must be placed inside a chip area so that no cells overlap and a target function is optimized. In standard cell placement all rectangles have the same width and the chip area is split into rows of equivalent width. Cells must be placed inside rows without overlaps and without exceeding row boundaries. A final solution is obtained using at least two stages. In the first stage, often called global placement, cells are distributed so as to optimize the target function. This initial distribution might violate problem constraints, therefore at a second stage often referred to as detailed placement cells are assigned to rows and overlaps are alleviated. In this paper we focus on heuristics in the context of iterative detailed placement whereby after assigning cells to rows, an iterative process further improves the optimization function, in our case wire length. The basis of the search mechanism is cell swapping. Through experimental evaluation we identify useful trade-offs between solution quality and execution time for the proposed search methods.