Paolo Amato

Ultra fast, two-bit ECC for Emerging Memories

Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct a few errors in just a few nanoseconds; for example to cope with failure mechanisms that could arise in new storage physics. Fast ECCs are also desired for eXecuted-in-Place (XiP) and DRAM applications. This paper shows the key elements to implement a BCH code able to correct 2 errors in a page of 256 data bits in no more than 10ns with 180nm-CMOS logic, and with low energy consumption. The decoding time can be further reduced to few ns using smaller gate length logics. Moreover, the proposed solution is soundly rooted in BCH theory, and can be applied to any user data size. Basically the ideas are to avoid the division in the computation of the coefficients of the Error Locator Polynomial (ELP) of the BCH code, to optimize the implementation of the multiplication in the Galois Fields (GF) and to fully implement the decoder in a parallel combinatorial architecture. Such a BCH code has been embedded in a 45nm 1Gbit Phase Change Memory (PCM) device.

Fast Decoding ECC for Future Memories

High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore, we propose an architecture for fast decoding of double and triple ECCs. In our architecture, any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular, the error locator polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here, we describe a gate-level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.

An Analytical Model of eMMC Key Performance Indicators

Embedded Multi Media Card (eMMC) has become the mainstream embedded storage system for mobile devices like Smartphones and Tablets and it is gaining traction in other products (e.g. Wearables) and segments (e.g. Automotive). eMMC devices are complex embedded systems that include one or more Flash NAND chips and a microcontroller with a specific Firmware (FW). Estimating eMMC key performance indicators (KPIs) since the early stage of the product definition is paramount to identify potential gaps, and give prompt feedbacks to development teams. In this paper a sound theoretical framework for estimating eMMC system metrics is introduced. The mathematical model takes into account the most relevant architectural parameters of NANDs, microcontroller and FW.

Mobile Memory Systems

The mobile market will continue to drive the memory industry in the up-coming years, with the highest growth for both system memory and storage. It is expected that handsets and tablets will represent more than 40% of DRAM and NANDindustry bit demand in 2018. The evolution from feature phones to smartphones and tablets imposed a steady improvement to memory system in terms of interfaces, performances and features, to address the challenging requirements of new applications.After a brief description of smartphone architecture, this paper summarizes features and characteristics of the memory devices in todays mobile systems describing their evolution in the recent years. Furthermore, it illustrates usage models and typical workloads measured in smartphones. Some relevant use cases where the memory system plays a fundamental role for the user experience are described, including high resolution photo and video, and gaming.