Parhat Ahmet

Annealing Reaction for Ni Silicidation of Si Nanowire

Silicidation of Si Nanowire (Si NW) has been investigated. In order to estimate the activation energy for Ni silicide of Si NW, the encroachment length of Ni silicide from the edge of exposed Si NW was measured by SEM images. The activation energy of Ni silicidation into 12nm x 17nm (110) Si NW was 0.95eV. Similarly, the activation energy of Ni silicidation into 8nm x 12nm (100) Si NW was 0.90eV. They are smaller than 1.23eV [1] which is the activation energy of Ni silicidation for (100) bulk S

Analysis of threshold voltage variations of FinFETs relating to short channel effects

Clarification of robustness for threshold voltage (Δth) variation in FinFETs is very important. Vth variation (ΔVth) caused by fluctuations of some principal device parameters are evaluated, compared to the planar MOSFETs. However, the origin of ΔVth is complex in short channel devices due to contribution of short channel effects (SCEs). Therefore, the origin of ΔVth is separated into two factors, that is, intrinsic factor which can be determined by Poissons equation along M-O-S stack, called the 1D factor, and factors caused by SCEs, called 2D factors. The ΔVth is dominated by both factors on the planar MOSFETs, while it is dominated by the 2D factor on the FinFETs because the amount of spacer charge in the channel is small. Additionally, the Vth is studied in two advanced FinFET structures which show reduced SCEs.

Parasitic Effects Depending on Shape of Spacer Region on FinFETs

Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer region. The trade-off relationship between these two parasitic elements was demonstrated on the expansion of the fin width in the spacer region. The gate delay characteristic of the FinFETs was optimized by gradual expansion with triangular shape. It was indicated that not only parasitic resistance but also parasitic capacitance on the spacer region was significant for transistor performance.

Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness

A systematic study of the dependence of short-channel effects (SCEs) on the channel thickness (Tch) of double-gate MOSFETs revealed that there is a particular range of Tch in which SCEs are significantly degraded compared to those of conventional planar MOSFETs. This phenomenon was found to originate from the electric field penetrating the channel region from the drain due to the disappearance of a neutral region in the channel. This dependence of this phenomenon on device parameters such as the channel doping concentration (Nc), the equivalent oxide thickness (EOT) and the gate length (Lg) was examined. The degradation of SCEs due to an inappropriate Tch was found to become more significant as Nc and Lg are reduced.

Analysis of Threshold Voltage Variation in Fin Field Effect Transistors: Separation of Short Channel Effects

The variation in the threshold voltage caused by fluctuations in a device parameter is given by the product of a sensitivity coefficient and the fluctuation amount. In this paper, the sensitivity coefficient for each device parameter was separated into two factors: one due to an intrinsic mechanism [one-dimensional (1D) factor] and another due to short-channel effects [two-dimensional (2D) factor]. Using this concept, the variations in the threshold voltage and the sensitivity coefficients in doped fin field effect transistors (FinFETs), undoped FinFETs and planar metal–oxide–semiconductor FETs (MOSFETs), whose structures are based on the ITRS, were evaluated for the fluctuations in the principal device parameters. It was found that the 2D factor rather than the 1D factor dominated the sensitivity coefficients, although the degree of domination varies between the fluctuating parameters. The 1D and 2D factors were found to cancel each other out, thereby reducing the sensitivity coefficient. Based on these results, FinFETs with various structures were examined and controlling short-channel effects was demonstrated to be an effective way to reduce the variation in the threshold voltage.

Er inserted Ni silicide metal source/drain for Schottky MOSFETs

A Schottky barrier height modulation technique for achieving a low Schottky barrier height in Ni silicide metal source/drain by Er layer insertion was reviewed. The effectiveness and possibility of the technique was demonstrated by fabricating Schottky barrier source/drain MOSFETs onto both bulk and SOI substrates.

Fabrication of SB-MOSFETs on SOI Substrate Using Ni Silicide Containing Er Interlayer

SB-MOSFETs were fabricated on SOI substrates by applying novel Schottky barrier height modulation technique of Er interlayer insertion at the interface of Ni/Si prior to Ni silicidation process. It was found that Er interlayer insertion lowered Schottky barrier height for electrons while no significant increase of the resistivity in the Er interlayer inserted films compare to pure Ni silicide films in the annealing temperature range of 500-750 C. Effects of Er insertion to the transistor characteristics of SOI SB-MOSFETs are also discussed.

Analysis of Threshold Voltage Variations of FinFETs : Separation of Short Channel Effects and Space Charge Effects

effects and space charge effects Yusuke Kobayashi, Kazuo Tsutsui, Kuniyuki Kakushima, Parhat Ahmet, V. Ramgopal Rao and Hiroshi Iwai 1 Dept. of Electronics and Applied Physics, Tokyo Institute of Technology, 4259, Nagatsuta, Yokohama, Kanagawa 226-8502, Japan Phone: +81-45-924-5461 E-mail: kobayashi.y.am@m.titech.ac.jp 2 Frontier Research Center, Tokyo Institute of Technology, 4259, Nagatsuta, Yokohama, Kanagawa 226-8502, Japan 3 Dept. of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai-400076, Powai, India

Parasitic Effects in Multi-Gate MOSFETs

The parasitics in multi-gate transistors (MugFETs or FinFETs) are expected to significantly degrade the device and circuit performance in scaled technologies. Using extensive 3-D device and circuit simulations, the impact of parasitics on the device and circuit performance is systematically investigated. The results clearly identify the issues in integrating high-K gate dielectrics in scaled multi-gate transistors. We show from 3-D simulations that, when a high-K gate dielectric (with a K ~ 15, similar to hafnium oxide) is integrated in a multi-gate transistor, a 5times increase (compared to the SiO2) in the off current occurs due to the fringing field induced barrier lowering effects. At the circuit level, our results show that, an order of magnitude degradation in the delay can take place, due to the unoptimized FinFET layouts.