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Dive into the research topics where Kenji Natori is active.

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Featured researches published by Kenji Natori.


Journal of Applied Physics | 1994

Ballistic metal‐oxide‐semiconductor field effect transistor

Kenji Natori

Experiments on ultra‐small metal‐oxide‐semiconductor field effect transistors (MOSFETs) less than 100 nm have been widely reported recently. The frequency of carrier scattering events in these ultra‐small devices is diminished, so that further suppression of carrier scattering may bring these devices close to the regime of ballistic transport. Carrier scattering is suppressed by constructing their channel regions with intrinsic Si and also by low temperature operation. This article proposes the ballistic transport of carriers in MOSFETs, and presents the current‐voltage characteristics of the ballistic n‐channel MOSFET. The current is expressed with the elementary parameters without depending on the carrier mobility. It is independent of the channel length and is proportional to the channel width. The current value saturates as the drain voltage is increased and the triode and the pentode operation are specified as in the conventional MOSFET. Similar current‐voltage characteristics in the ballistic transp...


Applied Physics Letters | 1998

Thickness dependence of the effective dielectric constant in a thin film capacitor

Kenji Natori; Daijiro Otani; Nobuyuki Sano

The static value of the effective dielectric constant in a thin film capacitor is simulated by means of the local field theory. The value of it shows a sharp decrease as the film thickness is decreased in an ultrathin film geometry. This phenomenon is due to the size effect intrinsic to a thin film structure and has nothing to do with the material aspect. The decrease is more remarkable for larger values of the bulk dielectric constant. It is recovered by inserting interface layers with larger atomic polarizability between the film and the capacitor electrode.


Journal of Applied Physics | 2005

Characteristics of a carbon nanotube field-effect transistor analyzed as a ballistic nanowire field-effect transistor

Kenji Natori; Yoji Kimura; Tomo Shimizu

A general expression of the current–voltage characteristics of a ballistic nanowire field-effect transistor (FET) is derived. At T=0, the conductance, which is equal to the quantum conductance multiplied by the number of channels at zero bias, decreases stepwise toward current saturation as the drain bias is increased. The current–voltage characteristics of a single-wall carbon nanotube FET in ballistic conduction are discussed based on the band structure of the nanotube. When both the gate overdrive and the drain bias are equal to 1V, the device made of a (19,0) nanotube and a 2-nm high-k gate insulator (e=40e0) flows a current of 183μA, which amounts to a current density 48 times as large as the counterpart of a silicon device. The high performance originates from a high carrier density due to the enhanced gate capacitance, and a large carrier velocity caused by the large group velocity of the original graphene band. Quantum capacitance also plays an important role in the device’s characteristics.


IEEE Electron Device Letters | 2002

Ballistic MOSFET reproduces current-voltage characteristics of an experimental device

Kenji Natori

The ballistic MOSFET characteristics are compared in detail with those of the experimental 70-nm device at low temperatures reported by Sai-Halasz et al. (1987). The saturated region characteristics for V/sub G//spl les/0.8 V show good agreement and a proper consideration of higher subbands significantly improves agreement for V/sub G//spl ges/1.0 V. The discrepancy is large in the linear region due to carrier scattering. The carrier backscattering mechanism and the bias effect are discussed.


IEEE Transactions on Electron Devices | 2012

EOT of 0.62 nm and High Electron Mobility in La-silicate/Si Structure Based nMOSFETs Achieved by Utilizing Metal-Inserted Poly-Si Stacks and Annealing at High Temperature

Takamasa Kawanago; Yeonghun Lee; Kuniyuki Kakushima; Parhat Ahmet; Kazuo Tsutsui; Nobuyuki Sugii; Kenji Natori; Takeo Hattori; H. Iwai

This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to 1.6 × 1011 cm-2eV-1 by annealing at 800 °C for 30 min in forming gas ambient, whereas excess silicate reaction concurrently induced a significant increase in EOT. By utilizing metal-inserted poly-Si (MIPS) stacks and their annealing at high temperature, the increase in EOT is drastically suppressed. At the same time, a superior interfacial property is obtained because the Si layer in the MIPS stacks prevents the excess oxygen diffusion from the atmosphere during the annealing process. As a result, the effective electron mobility of 155 cm2/V·s at 1 MV/cm and an EOT of 0.62 nm are successfully achieved by utilizing direct-contact La-silicate/Si structure. This result is comparable with the recorded effective electron mobility achieved by utilizing Hf-based oxides/Si structure. This demonstrates the advantage of our proposed method to realize the scaled EOT with a superior interfacial property for state-of-the-art metal-oxide-semiconductor field-effect transistors.


Journal of Applied Physics | 1998

Scaling limit of digital circuits due to thermal noise

Kenji Natori; Nobuyuki Sano

The error probability at a node of a digital circuit exposed to thermal noise agitation is investigated and the minimal dissipation–reliability relation for practical electronic circuits is derived. The digital circuit is modeled by an inverter chain with ideal transfer characteristics, and the error probability due to spurious data transfer caused by the thermal noise fluctuation is evaluated as a function of the node switching energy. The maximal error probability at each node allowed by the reliability requirement of the total system leads us to the minimal node energy dissipated per logical switching, which amounts to around 12 eV in the future 1010 gate system operated at a 10 GHz clock rate with a 104 FIT level reliability. In view of the device size-scaling trend of large-scale integrated circuits, the minimal node energy is expected to be reached at a feature size of 10–20 nm.


Journal of Applied Physics | 2006

Dielectric properties of hydrogen-terminated Si(111) ultrathin films

Jun Nakamura; Shunsuke Ishihara; Akiko Natori; Tomo Shimizu; Kenji Natori

Dielectric properties of Si(111) ultrathin films have been investigated using first-principles ground-states calculations in external electrostatic fields. With increasing thickness of Si(111) ultrathin films, the optical dielectric constant evaluated at the center of the slab converges to the experimental bulk dielectric constant at a thickness of only eight bilayers, while the energy gap of the slab is still larger than that of bulk Si. The converged theoretical dielectric constant for bulk Si is only 6.2% higher than the experimental one. Furthermore, spatial variations of the dielectric constant have also been evaluated using the position-dependent macroscopic field given by a clear-cut definition. The results show that the dielectric constant is reduced distinctly at the first few bilayers from the surface, which stems from the penetration of depolarized charges induced at the surface. Such an effective reduction of the depolarization field near the surface is one of the reasons for the decrease in o...


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1996

Full-band-structure theory of high-field transport and impact ionization of electrons and holes in Ge, Si, and GaAs

Massimo V. Fischetti; Nobuyuki Sano; S. E. Laux; Kenji Natori

The empirical pseudopotential band-structure of Ge, Si, and GaAs is used to compute the impact ionization (pair production) rate for electrons and holes. The constant-matrix-element and Kanes random-k approximations are also employed, to assess the importance of the energy-dependence of the Coulomb matrix element, of momentum conservation, and of the joint density of states. For electrons in Si and electrons and holes in Ge and GaAs, the latter is found to be dominant, while for holes in Si momentum conservation appears to be an important constraint on ionization processes near threshold. These results are then fitted to an isotropie ionization rate, function of carrier energy only. Full-band-structure Monte Carlo simulations are finally performed in order to calibrate the acoustic and nonpolar-optical deformation potentials. The low-energy deformation potentials are obtained from the usual1 fits to experimental velocity-field characteristics, while high-energy deformation potentials are determined from fits to experimental data on the ionization coefficients. The usual ambiguity of conventional Monte Carlo calibration of the scattering parameters ∼ using both carrier-phonon and impact ionization rates as fitting entities ∼ is thus removed, giving us better confidence on the final result. The deformation potentials so obtained are in good agreement with those reported in the literature, whenever a comparison is meaningful.


IEEE Transactions on Electron Devices | 2012

Compact Modeling of Quasi-Ballistic Silicon Nanowire MOSFETs

Kenji Natori

A compact model for the quasi-ballistic silicon nanowire MOSFET was developed by supplementing the ballistic framework previously disclosed by us with an original carrier-scattering model. The scattering model considers elastic scattering and optical phonon emission, which is the dominant route of energy relaxation in the device. The quasi-ballistic electric current showed a remarkable decrease compared with the ballistic counterpart. The relative decrease or “ballisticity” gradually improved when the channel length was reduced, but the value remained considerably less than the ballistic limit, even in the limit of zero channel length. The transport physics underlying the device characteristics is discussed.


Japanese Journal of Applied Physics | 2003

Multi-Subband Effects on Performance Limit of Nanoscale MOSFETs

Kenji Natori; Tomo Shimizu; Tsuyoshi Ikenobe

Multi-subband effects on the performance limit of metal oxide semiconductor field effect transistors (MOSFETs), which is represented by the ballistic MOSFET characteristics, is discussed for room temperature operation. A compact formula of the drain current of ballistic MOSFETs has been derived by the effective one-subband approximation. Consideration of the multi-subband effect, which requires a complicated self-consistent calculation, revises the result and provides a rigorous current value 20% smaller than the conventional estimation. The injection velocity ranges over a narrow region of 1.2–1.6×107 cm/s. It is equal to the thermal velocity in the weak inversion, but it increases in the strong inversion due to carrier degeneracy. A compact expression for predicting the saturation drain current is derived. The mechanism of current reduction due to the multi-subband effect is discussed.

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Kazuo Tsutsui

Tokyo Institute of Technology

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Nobuyuki Sugii

Tokyo Institute of Technology

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Kuniyuki Kakushima

Tokyo Institute of Technology

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Hiroshi Iwai

Tokyo Institute of Technology

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Parhat Ahmet

Tokyo Institute of Technology

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Hiroshi Iwai

Tokyo Institute of Technology

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Takamasa Kawanago

Tokyo Institute of Technology

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