Nobuyuki Sugii

Role of Si1−xGex buffer layer on mobility enhancement in a strained-Si n-channel metal–oxide–semiconductor field-effect transistor

Strained-Si n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated on molecular-beam epitaxially grown strained Si with various Si1−xGex buffer layers. Effective electron mobility in n-MOSFETs with a Si1−xGex (x=0.2, 0.3) graded buffer layer was 60% higher than that in an unstrained-Si n-MOSFET. However, mobility of samples with a Si1−xGex buffer layer on a low-temperature grown Si buffer layer was not increased as much as that of samples on a graded buffer layer. Atomic-force microscopic observation suggests that the power spectrum of surface roughness of the strained-Si layer varies according to the buffer layer, and this variation may affect the enhancement of mobility.

Local

The silicon on thin buried oxide (SOTB) has the smallest V th variation among planar CMOS due to a low-dose channel. This study focuses on evaluating local variability components and searching for the dominant factor after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity is important to reduce both the global and local variations. The local V th variation A Vt was very small, ~ 1.0 and 0.7 mV·¿m for NMOS and PMOS, respectively; however, additional unknown factors other than RDF still exist. Silicon-on-insulator thickness variation does not play a major role in ¿V th , and the SOTB is scalable to less than 25 nm while maintaining small variability and, hence, low power consumption. The larger variability in NMOS compared to that in PMOS cannot be explained by conventional RDF but seems to be strongly related to channel doping.

V_{\rm th}

Characteristic variations of fully depleted silicon-on-insulator (SOI) MOSFETs with extremely thin buried oxide are examined by device simulations. It is found, for the first time, that a SOI device with low channel impurity concentration and high substrate concentration has high immunity to both parameter variations and random dopant fluctuations (RDFs). Fully depleted (FD) silicon-on-insulator (SOI) MOSFET, random dopant fluctuation (RDF), thin buried oxide (BOX), variability.

Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

Chemical-mechanical-polishing (CMP) was used to smooth the surface of a SiGe substrate, on which strained-Si n- and p-MOSFETs were fabricated. By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, namely, to 0.4 nm (rms). A strained-Si layer was then successfully grown on the CMP-treated SiGe substrate. The fabricated strained-Si MOSFETs showed good turn-off characteristics, (i.e., equivalent to those of Si control devices). Moreover, capacitance-voltage (CV) measurements revealed that the quality of the gate oxide of the strained-Si devices was the same as that of the Si control devices. Flat-band and threshold voltages of the strained-Si devices were different from those of the Si control devices mainly due to band discontinuity. Electron and hole mobilities of strained-Si MOSFETs under a vertical field up to 1.5 MV/cm increased by 120% and 42%, respectively, compared to the universal mobility. Furthermore, current drive of the n- and p-MOSFETs (L/sub eff//spl ges/0.3 /spl mu/m) was increased roughly by 70% and 50%, respectively. These improvements in characteristics indicate that CMP of the SiGe substrate is a critical technique for developing high-performance strained-Si CMOS.

Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX

Thermal stability of the strained-Si/Si0.7Ge0.3 heterostructure was investigated by secondary-ion mass spectroscopy, Raman spectroscopy, and atomic force microscopy. Ge atoms diffused out through the strained-Si layer during heat treatment of 1000 °C for 1 h. The activation energy of Ge diffusion in strained Si was 3.3 eV, which was lower than the value in unstrained Si (4.7–5.3 eV). Strain in the strained-Si layer did not change after thermal treatment at 950 °C or less for 1 h. Slip lines due to strain relaxation formed at the surface of the strained-Si layer for the samples treated at 950–1000 °C for 1 h. For practical application of the strained-Si/Si0.7Ge0.3 heterostructure to electron devices, the maximum thermal budget should be made less than that equivalent to 900 °C annealing for 1 h.

Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Solid-phase crystallization of Si1−xGex (x=0–1.0) alloy layers deposited on a Si (100) substrate was investigated by ellipsometric spectroscopy. From a dispersion analysis of dielectric spectra, we deduced a crystallinity corresponding to the degree of average lattice alignment of the composed polycrystalline Si1−xGex layers and investigated the dynamical change in crystallinity during crystallization. We found that the crystallinity and crystallization temperature (TC) rapidly decreased with increasing Ge concentration (x). When x was small (=0–0.3), the highest crystallinity was ∼0.8 of that for single crystals while the lowest one was considerably below 0.6 when x>0.8. Moreover, the crystallinity decreased with increasing temperature above TC. We investigated the nucleation rate during crystallization and found that the decrease in crystallinity at both large Ge concentration and high temperature can be explained by a trade-off between the nucleation and crystallization rates; nucleation was dominant u...

Thermal stability of the strained-Si/Si0.7Ge0.3 heterostructure

The Silicon on Thin BOX (SOTB) has the smallest Vth variation among planar CMOS due to low-dose channel. This study focused on identifying the remaining components after reducing random-dopant fluctuation (RDF) by decreasing impurities in the channel. Improving short-channel-effect immunity and body-thickness uniformity is the key to further reducing the variation. An often mentioned phenomenon, larger variability in NMOS than PMOS, cannot be explained by conventional RDF but is surely related to channel doping.

Solid-phase crystallization of Si1−xGex alloy layers

Ultra-thin single crystal silicon with the (100) surface formed by the local-oxidation-of-silicon (LOCOS) on a silicon-on-insulator (SOI) substrate becomes a quasi-direct band-gap semiconductor due to the quantum mechanical confinement effect. The device is a simple pn diode in a planar structure. Electro-luminescence (EL) has been observed by the lateral carrier injections into the two-dimensional quantum well.

Comprehensive study on vth variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation

A ldquosilicon on thin BOXrdquo (SOTB) CMOS with a 50-nm single metal (FUSI) gate has been developed. By employing an intrinsic channel and a metal gate, this SOTB achieves the smallest Vth variability ever reported. The measured Pelgrom coefficients of the SOTB were 1.8 and 1.5 for NMOS and PMOS, respectively, even in the case of relatively thick EOT of 1.9 nm. Both multi-Vth control as well as suppression of short-channel effects were carried out simply by adjusting the impurity concentration beneath the BOX layer while keeping the channel almost intrinsic. Inverter delay and off-current were optimized by controlling gate-overlap length by means of a dual-layer offset spacer. It is shown that, within planar-type low-power CMOS devices, the SOTB is the most scalable because of its capability of multi-Vth and excellent matching characteristics.

Electro-luminescence from ultra-thin silicon

The authors propose a light-emitting field-effect transistor with the active layer made of the ultrathin single crystal silicon with the (100) surface orientation. The ambipolar carrier injections from the highly impurity doped regions to the ultrathin silicon are achieved in complementary-metal-oxide-semiconductor compatible planar structures and the optical intensities are controlled by the gate voltage. By using the device, they have demonstrated that a simple electrical signal can be transferred by light and detected on the same silicon chip as photocurrents controlled by the gate bias.