Patrice Garcia

Nanoscale CMOS Transceiver Design in the 90–170-GHz Range

This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately + 2 dBm and a phase noise of -90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1/f noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

A Passive W-Band Imaging Receiver in 65-nm Bulk CMOS

A passive imaging receiver operating in the W-band around 90 GHz has been realized in a digital 65-nm CMOS process. The circuit, occupying only 0.41 mm2, integrates an SPDT switch with 4.2 dB loss and 25 dB isolation, a five-stage telescopic cascode LNA with 27 dB gain at 90 GHz, and a W-band square-law detector, all consuming less than 33 mA from 1.2 V. A version of the receiver without the input SPDT switch has a peak responsivity of over 200 kV/W and a minimum NEP of less than 0.1 pW/ Hz. The full Dicke radiometer, which includes the input switch, achieves a responsivity of 90 kV/W and an NEP of 0.2 pW/ Hz. This work represents the first W-band passive imaging receiver to be implemented in standard CMOS with this level of integration.

A Low-Voltage SiGe BiCMOS 77-GHz Automotive Radar Chipset

This paper presents a complete 2.5-V 77-GHz chipset for Doppler radar and imaging applications fabricated in SiGe HBT and SiGe BiCMOS technologies. The chipset includes a 123-mW single-chip receiver with 24-dB gain and an IP1 dB of -21.7 dBm at 76-GHz local oscillator (LO) and 77-GHz RF, 4.8-dB double-sideband noise figure at 76-GHz LO and 1-GHz IF, and worst case -98.5 dBc/Hz phase noise at 1-MHz offset over the entire voltage-controlled oscillator tuning range at room temperature. Monolithic spiral inductors and transformers result in a receiver core area of 450 mum times 280 mum. For integration of an entire 77-GHz transceiver, a power amplifier with 19-dB gain, +14.5-dBm saturated output power, and 15.7% power-added efficiency is demonstrated. Frequency divider topologies for 2.5-V operation are investigated and measurement results show a 105-GHz static frequency divider consuming 75 mW, and a 107-GHz Miller divider consuming 33 mW. Measurements on all circuits confirm operation up to 100 deg C. Low-power low-noise design techniques for each circuit block are discussed.

A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS

This paper presents a fully integrated receiver, with LNA, mixer, IF amplifier, fundamental-frequency quadrature VCO, and static frequency divider, operating at 95GHz in a 65nm general-purpose (GP) CMOS technology. The receiver consumes 206mW from a 1.2V/1.5V supply. With large RF and IF bandwidths of over 19GHz and 16GHz, respectively, it is suitable for passive-imaging applications, and for wireless chip-to-chip communication at data-rates exceeding 20Gb/s. Together with the recently reported 60GHz receiver in 90nm CMOS, this 95GHz receiver in 65nm CMOS demonstrates that scaling of entire mm-wave receivers is possible in both frequency coverage and across technology nodes.

A SiGe:C BiCMOS WCDMA zero-IF RF front-end using an above-IC BAW filter

The feasibility of a fully integrated RF front-end using an above-IC BAW integration technique is demonstrated for WCDMA applications. The circuit has a voltage gain of 31.3dB, a noise figure of 5.3dB, an in-band IIP3 of -8dBm and IIP2 of 38dBm, with a total power consumption of 36mW. The BAW filter area is 0.45mm/sup 2/ and the total circuit area including the BAW filter is 2.44mm/sup 2/.

W-band 65-nm CMOS and SiGe BiCMOS transmitter and receiver with lumped I-Q phase shifters

This paper describes 80–94 GHz and 70–77 GHz I-Q phase shifters and the corresponding transmitter and receiver ICs, fabricated in 65-nm CMOS and SiGe BiCMOS technologies, respectively. Lumped inductors and transformers are employed to realize small-form factor 90° hybrids as needed in high density phased arrays. The CMOS transmitter operates with a saturated output power of +3 dBm and exhibits maximum absolute phase and amplitude errors of 14° and 5.5 dB, respectively, when the phase is varied from 0° to 360° in steps of 22.5°. The absolute phase error in the SiGe BiCMOS receiver is less than 8°, with a maximum gain imbalance below 3 dB over its 3-dB bandwidth of 70–77 GHz. The peak gain and power consumption are 3.8 dB and 142 mW from 1.2V supply for the CMOS transmitter, and 17 dB and 128 mW from 1.5V and 2.5V supplies for the SiGe BiCMOS receiver.

65-nm CMOS, W-Band Receivers for Imaging Applications

Two 76-92 GHz receivers, featuring 3-stage cascode LNAs coupled through a transformer to a double-balanced Gilbert-cell mixer and differential DC-5GHz IF buffer, are reported in 65-nm general purpose (GP) CMOS technology. One receiver features a traditional LNA with series-series inductive feedback, while the LNA of the second receiver employs a shunt-series, transformer-feedback cascode stage. Both receivers have a differential down-conversion gain of 12 dB, an input P1dB of -13 dBm, and a double-sideband noise figure of 9-10 dB. They each occupy an area of 550 mum times 550 mum and consume 94 mW. An LO-to-RF isolation of 60 to 59 dB was measured for LO signals in the 80-85 GHz range. The transformer-feedback provides a broader bandwidth input match, lower than -10 dB from 74 to 95 GHz.

Design of a Dual W- and D-Band PLL

This paper describes the design considerations and performance of the highest frequency phase-locked loop (PLL) reported to date. The PLL was fabricated in a 0.13-μm SiGe BiCMOS process and integrates on a single die: a fundamental-frequency 86-92 GHz Colpitts voltage-controlled oscillator (VCO), a differential push-push 160-GHz Colpitts VCO with two differential outputs at 80 GHz, a programmable divider chain, the charge pump, and all loop filter components. It achieves the lowest W- and D-band phase noise of -93 dBc/Hz at 90 GHz and -87.5 dBc/Hz at 163 GHz, both measured at a 100 kHz offset, and demonstrates an extended locking range of 80-100 GHz at the fundamental frequency, and 160-169 GHz at the second harmonic output of the push-push VCO. The single-ended PLL output power is -3 dBm at 90 GHz and -25 dBm at 164 GHz. The chip consumes 1.25 W from 1.8 V, 2.5 V, and 3.3 V supplies and occupies 1.1 mm × 1.7 mm, including pads.

A 94GHz SPST Switch in 65nm Bulk CMOS

A 3-bit lumped SPST switch that operates from DC to greater than 94 GHz has been realized in 65 nm CMOS. At 94 GHz, it provides an insertion loss of 1.6 dB and an isolation of over 30 dB. Power-handling measurements of the switch at 60 GHz show no sign of input compression up to an equipment-limited input power of +9 dBm. The circuit was demonstrated as a digitally controlled variable attenuator and as a transmit-receive switch in an array of three 94 GHz transceivers. In the latter case, the on-chip loop-back of PA signals into the LNA in each individual transceiver is possible, enabling the production testing of mm-wave transceiver functionality at IF without the requirement for high-speed signal sources or probes. Measurements of the transmit-receive switch show a return-loss better than -8 dB from 58 to 94 GHz.

Advanced SiGe BiCMOS and CMOS platforms for Optical and Millimeter-Wave Integrated Circuits

This paper presents the status of most advanced CMOS and BiCMOS technologies able to address very high-speed optical communications and millimeter-wave applications. The performance of active and passive devices available on bulk Si and high-resistivity SOI is reviewed and HF characteristics of state-of-the-art SiGe HBTs and MOSFETs are compared. The performance of building blocks designed in different CMOS and BiCMOS platforms are also presented. Finally, we conclude on the suitability of different Si technologies to address such high-frequency applications